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ISL12020M View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12020M Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving Intersil
Intersil Intersil
ISL12020M Datasheet PDF : 32 Pages
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ISL12020M
VDD
VTRIP
VBAT
VBAT - VBATHYS
BATTERY-BACKUP
MODE
2.2V
1.8V
VBAT + VBATHYS
FIGURE 12. BATTERY SWITCHOVER WHEN
VBAT < VTRIP
VDD
VBAT
VTRIP
BATTERY-BACKUP
MODE
3.0V
2.2V
VTRIP
VTRIP + VTRIPHYS
FIGURE 13. BATTERY SWITCHOVER WHEN
VBAT > VTRIP
The I2C bus is deactivated in battery-backup mode to
reduce power consumption. Aside from this, all RTC
functions are operational during battery-backup mode.
Except for SCL and SDA, all the inputs and outputs of
the ISL12020M are active during battery-backup mode
unless disabled via the control register.
The device Time Stamps the switchover from VDD to
VBAT and VBAT to VDD, and the time is stored in tSV2B
and tSB2V registers respectively. If multiple VDD
power-down sequences occur before status is read, the
earliest VDD to VBAT power-down time is stored and the
most recent VBAT to VDD time is stored.
Temperature conversion and compensation can be
enabled in battery-backup mode. Bit BTSE in the BETA
register controls this operation, as described in “BETA
Register (BETA)” on page 19.
Power Failure Detection
The ISL12020M provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost
all power to the device (both VDD and VBAT).
Brownout Detection
The ISL12020M monitors the VDD level continuously and
provides warning if the VDD level drops below prescribed
levels. There are six (6) levels that can be selected for
the trip level. These values are 85% below popular VDD
levels. The LVDD bit in the Status Register will be set to
“1” when brownout is detected. Note that the I2C serial
bus remains active unless the Battery VTRIP levels are
reached.
Battery Level Monitor
The ISL12020M has a built in warning feature once the
Back Up battery level drops first to 85% and then to 75%
of the battery’s nominal VBAT level. When the battery
voltage drops to between 85% and 75%, the LBAT85 bit
is set in the status register. When the level drops below
75%, both LBAT85 and LBAT75 bits are set in the status
register.
The battery level monitor is not functional in battery
backup mode. In order to read the monitor bits after
powering up VDD, instigate a battery level measurement,
which is set by setting the TSE bit to "1" (BETA register),
and then read the bits.
There is a Battery Time Stamp Function available. Once
the VDD is low enough to enable switchover to the
battery, the RTC time/date are written into the TSV2B
register. This information can be read from the TSV2B
registers to discover the point in time of the VDD
power-down. If there are multiple power-down cycles
before reading these registers, the first values stored in
these registers will be retained. These registers will hold
the original power-down value until they are cleared by
setting CLRTS = 1 to clear the registers.
The normal power switching of the ISL12020M is
designed to switch into battery-backup mode only if the
VDD power is lost. This will ensure that the device can
accept a wide range of backup voltages from many types
of sources while reliably switching into backup mode.
Note that the ISL12020M is not guaranteed to operate
with VBAT < 1.8V. If the battery voltage is expected to
drop lower than this minimum, correct operation of the
device, especially after a VDD power-down cycle, is not
guaranteed.
The minimum VBAT to insure SRAM is stable is 1.0V.
Below that, the SRAM may be corrupted when VDD
power resumes.
Real Time Clock Operation
The Real Time Clock (RTC) uses an integrated 32.768kHz
quartz crystal to maintain an accurate internal
representation of second, minute, hour, day of week,
date, month, and year. The RTC also has leap-year
correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24-hour or
AM/PM format. When the ISL12020M powers up after the
loss of both VDD and VBAT, the clock will not begin
incrementing until at least one byte is written to the clock
register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing
Single Event or interrupt alarm mode is selected via the
IM bit. Note that when the frequency output function is
enabled, the alarm function is disabled.
The standard alarm allows for alarms of time, date,
day of the week, month, and year. When a time alarm
occurs in single event mode, the IRQ/FOUT pin will be
pulled low and the alarm status bit (ALM) will be set
to “1”.
11
FN6667.4
February 11, 2010
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