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ISL12020M View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
ISL12020M Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving Intersil
Intersil Intersil
ISL12020M Datasheet PDF : 32 Pages
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ISL12020M
The pulsed Interrupt mode allows for repetitive or
recurring alarm functionality. Hence, once the alarm is
set, the device will continue to alarm for each occurring
match of the alarm and present time. Thus, it will alarm
as often as every minute (if only the nth second is set) or
as infrequently as once a year (if at least the nth month
is set). During pulsed Interrupt mode, the IRQ/FOUT pin
will be pulled low for 250ms and the alarm status bit
(ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit).
The alarm function can be enabled/disabled during
battery-backup mode using the FOBATB bit. For more
information on the alarm, please see “ALARM Registers
(10h to 15h)” on page 21.
Frequency Output Mode
The ISL12020M has the option to provide a clock output
signal using the IRQ/FOUT open drain output pin. The
frequency output mode is set by using the FO bits to
select 15 possible output frequency values from 1/32Hz
to 32kHz. The frequency output can be enabled/disabled
during battery-backup mode using the FOBATB bit.
General Purpose User SRAM
The ISL12020M provides 128 bytes of user SRAM. The
SRAM will continue to operate in battery-backup mode.
However, it should be noted that the I2C bus is disabled
in battery-backup mode.
I2C Serial Interface
The ISL12020M has an I2C serial bus interface that
provides access to the control and status registers and
the user SRAM. The I2C serial interface is compatible
with other industry I2C serial bus protocols using a
bi-directional data signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL12020M provides both initial timing correction
and temperature correction due to variation of the
crystal oscillator. Analog and digital trimming control is
provided for initial adjustment, and a temperature
compensation function is provided to automatically
correct for temperature drift of the crystal. Initial values
for the initial AT and DT settings (ITR0), temperature
coefficient (ALPHA), crystal capacitance (BETA), as well
as the crystal turn-over temperature (XTO), are preset
internally and recalled to RAM registers on power-up.
These values can be overwritten by the user
although this is not suggested as the resulting
temperature compensation performance will be
compromised. The compensation function can be
enabled/disabled at any time and can be used in battery
mode as well.
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to
addresses [00h:2Fh]. The defined addresses and default
values are described in the Table 1. The battery backed
general purpose SRAM has a different slave address
(1010111x), so it is not possible to read/write that
section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by
performing a byte or a page write operation directly to
any register address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address
16h to 1Ah.
5. Time Stamp for VDD Status (5 bytes): Address 1Bh
to 1Fh.
6. Daylight Savings Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah,
2Bh
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
10.Crystal ALPHA at high temperature, ALPHA_H (1
byte): 2Dh
11.Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h
to 06h) only when the WRTC bit (bit 6 of address 08h) is
set to “1”. A multi-byte read or write operation
should be limited to one section per operation for
best RTC timekeeping performance.
A register can be read by performing a random read at
any address at any time. This returns the contents of
that register location. Additional registers are read by
performing a sequential read. For the RTC and Alarm
registers, the read instruction latches all clock registers
into a buffer, so an update of the clock does not change
the time being read. At the end of a read, the master
supplies a stop condition to end the operation and free
the bus. After a read, the address remains at the
previous address +1 so the user can execute a current
address read and continue reading the next register.
When the previous address is 2Fh, the next address will
wrap around to 00h.
It is not necessary to set the WRTC bit prior to writing
into the control and status, alarm, and user SRAM
registers.
12
FN6667.4
February 11, 2010
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