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IS25LQ032C View Datasheet(PDF) - Integrated Silicon Solution

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IS25LQ032C
REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and BP3, BP2, BP1, BP0 bits: The Block Protection (BP3,
Status Register Bit Definitions.
BP2, BP1 and BP0) bits are used to define the portion
of the memory area to be protected. Refer to Tables 7,
The BP0, BP1, BP2, BP3 and SRWD are non-volatile 8 and 9 for the Block Write Protection bit settings.
memory cells that can be written by a Write Status
When a defined combination of BP3, BP2, BP1 and
Register (WRSR) instruction. The default value of the BP0 bits are set, the corresponding memory area is
BP2, BP1, BP0, and SRWD bits were set to “0” at
protected. Any program or erase operation to that area
factory. The Status Register can be read by the Read will be inhibited.Note: a Chip Erase (CHIP_ER)
Status Register (RDSR). Refer to Table 10 for
instruction is executed only if all the Block Protection
Instruction Set.
Bits are set as “0”s.
The function of Status Register bits are described as
follows:
SRWD bit: The Status Register Write Disable (SRWD)
bits operates in conjunction with the Write Protection
WIP bit: The Write In Progress (WIP) bit is read-only, (WP#) signal to provide a Hardware Protection Mode.
and can be used to detect the progress or completion When the SRWD is set to “0”, the Status Register is
of a program or erase operation. When the WIP bit is not write-protected. When the SRWD is set to “1” and
“0”, the device is ready for a write status register,
the WP# is pulled low (VIL), the bits of Status Register
program or erase operation. When the WIP bit is “1”, (SRWD, BP3, BP2, BP1, BP0) become read-only, and
the device is busy.
a WRSR instruction will be ignored. If the SRWD is set
to “1” and WP# is pulled high (VIH), the Status Register
WEL bit: The Write Enable Latch (WEL) bit indicates can be changed by a WRSR instruction.
the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled, and all QE bit: The Quad Enable (QE) is a non-volatile bit in
write operations, including write status register, write the status register that allows Quad operation. When
configuration register, page program, sector erase,
the QE bit is set to “0”,the pin WP# and HOLD# are
block and chip erase operations are inhibited. When enable. When the QE bit is set to “1”, the pin IO2 and
the WEL bit is “1”, write operations are allowed. The IO3 are enable.
WEL bit is set by a Write Enable (WREN) instruction.
Each write register, program and erase instruction
WARNING: The QE bit should never be set to a 1
must be preceded by a WREN instruction. The WEL bit during standard SPI or Dual SPI operation if the
can be reset by a Write Disable (WRDI) instruction. It WP# or HOLD# pins are tied directly to the power
will automatically be the reset after the completion of a supply or ground.
write instruction.
Table 5. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
SRWD1 QE BP3 BP2 BP1
BP0
WEL
Default (flash bit)
0
0
0
0
0
0
0
* The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory.
Bit 0
WIP
0
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
8
08/20/2012
 

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