IS25LQ032C View Datasheet(PDF) - Integrated Silicon Solution

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IS25LQ032C

32Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LQ032C

DEVICE OPERATION (CONTINUED)

FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION

The FRDO instruction is used to read memory data on

two output pins each at up to a 104 MHz clock.

The FRDO instruction code is followed by three

address bytes (A23 – A0) and a dummy byte (8

clocks), transmitted via the SI line, with each bit

latched-in during the rising edge of SCK. Then the first

data byte addressed is shifted out on the SO and SIO

lines, with each pair of bits shifted out at a maximum

frequency fCT, during the falling edge of SCK. The first

bit (MSb) is output on SO, while simultaneously the

second bit is output on SIO.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRDO instruction. FRDO instruction

is terminated by driving CE# high (VIH). If a FRDO

instruction is issued while an Erase, Program or Write

cycle is in process (BUSY=1) the instruction is ignored

and will not have any effects on the current cycle

Figure 14. Fast Read Dual-Output Sequence

CE#

SCK

SI

0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31

...

INSTRUCTION = 0011 1011b

3 - BYTE ADDRESS

23 22 21

... 3 2 1 0

SO

HIGH IMPEDANCE

CE#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

IO0

HIGH IMPEDANCE

IO1

HIGH IMPEDANCE

6 42 06 42 06

DATA OUT 1

DATA OUT 2

7 53 17 5 317

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

20

08/20/2012

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