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MAX551AEUB View Datasheet(PDF) - Maxim Integrated

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MAX551AEUB Datasheet PDF : 12 Pages
First Prev 11 12
+3V/+5V, 12-Bit, Serial, Multiplying DACs
in 10-Pin µMAX Package
+5V (+3V)
C1
VDD
RFB OUT
REF
DGND
MAX551
MAX552 AGND
MAX4167
VOUT
+5V
(+3V)
AC
REFERENCE
INPUT
10k
10kMAX4166
VDD
OUT
REF
MAX551
MAX552
GND
+1.43V TO +12.6V
OUT
MAX6160
ADJ
MAX4167
106M
( ) ARE FOR MAX552
Figure 6. Single-Supply, Current Mode Operation
An advantage of voltage mode operation is that a neg-
ative reference is not required for a positive output.
Note that the reference input (OUT) must always be
positive and is limited to no more than 2V when VDD is
5V. The unipolar and bipolar circuits in Figures 3 and 4
can be converted to voltage mode.
Current Mode
Figure 6 shows the MAX551/MAX552 in a current out-
put configuration in which the output amplifier is pow-
ered from a single supply, and AGND is biased to
1.23V. With 0V applied to the REF input, the output can
be programmed from 1.23V (zero code) to 2.46V (full
scale). With 2.45V applied to REF, the output can be
programmed from 1.23V (zero code) to 0.01V (full
scale).
The MAX4166 op amp that drives AGND maintains the
1.23V bias as AGND’s impedance changes with the
DAC’s digital code, from high impedance (zero code)
to 7kminimum (full scale).
Using an AC Reference
In applications where reference voltage has AC signal
components, the MAX551/MAX552 have multiplying
capability within the reference input range of ±6V. If the
DAC and the output amplifier are operated with a single
( ) ARE FOR MAX552
Figure 7. Single-Supply AC Reference Input Circuit
supply voltage, then an AC reference input can be off-
set with the circuit shown in Figure 7 to prevent the
DAC output voltage from exceeding the output amplifi-
er’s negative output rail. The reference input’s typical
-3dB bandwidth is greater than 700kHz, as shown in
the Typical Operating Characteristics graphs.
Offsetting AGND
The MAX551/MAX552 provide separate AGND and
GND inputs in the µMAX package. With this package,
AGND can be biased above GND to provide an arbi-
trary nonzero output voltage for a “0” input code
(Figure 8).
Layout, Grounding, and Bypassing
Bypass VDD with a 0.1µF capacitor, located as close to
VDD and GND as possible. The ground pins (AGND
and GND) should be connected in a star configuration
to the highest quality ground available, which should be
located as close to the MAX551/MAX552 as possible.
Since OUT and the output amplifier’s noninverting input
are sensitive to offset voltage, nodes that are to be
grounded should be connected directly to a single-
point ground through a separate, low-resistance (less
than 0.2) connection. The current at OUT and AGND
varies with input code, creating a code-dependent
error if these terminals are connected to ground (or vir-
tual ground) through a resistive path.
Parasitic coupling of the signal from REF to OUT is an
error source in dynamic applications. This coupling is
normally a function of board layout and pin-to-pin pack-
age capacitance. Minimize digital feedthrough with
guard traces between digital inputs, REF, and OUT
pins.
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