Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Write Protect (WP) (NM24C05 Only)
If tied to VCC, PROGRAM operations onto the upper half (upper
2Kbit) of the memory will not be executed. READ operations are
possible. If tied to VSS, normal operation is enabled, READ/
WRITE over the entire memory is possible.
This feature allows the user to assign the upper half of the memory
as ROM which can be protected against accidental programming.
When write is disabled, slave address and word address will be
acknowledged but data will not be acknowledged.
This pin has an internal pull-down circuit. However, on systems
where write protection is not required it is recommended that this
pin is tied to VSS.
Device Selection Inputs A2, A1 and A0 (as
These inputs collectively serve as “chip select” signal to an
EEPROM when multiple EEPROMs are present on the same IIC
bus. Hence these inputs, if present, should be connected to VCC
or VSS in a unique manner to allow proper selection of an EEPROM
amongst multiple EEPROMs. During a typical addressing se-
quence, every EEPROM on the IIC bus compares the configura-
tion of these inputs to the respective 3 bit “Device/Page block
selection” information (part of slave address) to determine a valid
selection. For e.g. if the 3 bit “Device/Page block selection” is 1-
0-1, then the EEPROM whose “Device Selection inputs” (A2, A1
and A0) are connected to VCC-VSS-VCC respectively, is selected.
Depending on the density, only appropriate number of “Device
Selection inputs” are provided on an EEPROM. For every “Device
selection input” that is not present on the device, the correspond-
ing bit in the “Device/Page block selection” field is used to select
a “Page Block” within the device instead of the device itself.
Following table illustrates the above:
The NM24C04/05 supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the bus as
a transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24C04/05 will be considered a
slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figure 1 and Figure 2 on next
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The NM24C04/
05 continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this condition
has been met.
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C04/05 to place the device in
the standby power mode, except when a Write operation is being
executed, in which case a second stop condition is required after
tWR period, to place the device in standby mode.
Device Selection Inputs
Selecting Page Block
A0 and A1
A0, A1 and A2
Note that even when just one EEPROM present on the IIC bus,
these pins should be tied to VCC or VSS to ensure proper termina-
NM24C04/05 Rev. G