datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

NM24C04 View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
NM24C04 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM Fairchild
Fairchild Semiconductor Fairchild
NM24C04 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Write Cycle Timing
SCL
SDA
8th BIT
ACK
Note:
WORD n
STOP
CONDITION
tWR
START
CONDITION
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
DS500070-6
Typical System Configuration
VCC
VCC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Note: Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k)
Example of 16K of Memory on 2-Wire Bus
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF
VCC
DS500070-7
VCC
SDA
SCL
Device
NM24C02/03
NM24C04/05
NM24C08/09
NM24C16/17
NM24C04/05 Rev. G
VCC
VCC
VCC
VCC
NM24C02/03
A0 A1 A2 VSS
NM24C02/03
A0 A1 A2 VSS
NM24C04/05
A1 A2 VSS
NM24C08/09
A2 VSS
To To To
VSS VSS VSS
To To To
VCC VSS VSS
To To
VCC VSS
To
VCC
DS500070-8
Address Pins Present
A0
A1
A2
Yes
Yes
Yes
No
Yes
Yes
No
No
Yes
No
No
No
Memory Size
2048 Bits
4096 Bits
8192 Bits
16,384 Bits
# of Page
Blocks
1
2
4
8
6
www.fairchildsemi.com
Direct download click here

 

Share Link : 

All Rights Reserved © datasheetbank.com 2014 - 2020 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]