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NM24C04 View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
NM24C04 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM Fairchild
Fairchild Semiconductor Fairchild
NM24C04 Datasheet PDF : 14 Pages
First Prev 11 12 13 14
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Current Address Read
Internally the NM24C04/05 contains an address counter that
maintains the address of the last byte accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n + 1. Upon receipt of the slave address with R/W set to
one, the NM24C04/05 issues an acknowledge and transmits the
eight bit byte. The master will not acknowledge the transfer but
does generate a stop condition, and therefore the NM24C04/05
discontinues transmission. Refer to Figure 6 for the sequence of
address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
dummywrite operation. The master issues the start condition,
slave address with the R/W bit set to zero and then the byte
address it is to read. After the byte address acknowledge, the
master immediately issues another start condition and the slave
address with the R/W bit set to one. This will be followed by an
acknowledge from the NM24C04/05 and then by the eight bit byte.
The master will not acknowledge the transfer but does generate
the stop condition, and therefore the NM24C04/05 discontinues
transmission. Refer to Figure 7 for the address, acknowledge and
data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C04/05 continues to output data for each ac-
knowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" to the
beginning of the memory. NM24C04/05 continues to output data
for each acknowledge received. Refer to Figure 8 for the address,
acknowledge, and data transfer sequence.
Current Address Read (Figure 6)
S
T
S
Bus Activity:
A
SLAVE
T
Master
R ADDRESS
O
T
P
SDA Line
101 0
1
Bus Activity:
EEPROM
Random Read (Figure 7)
S
T
Bus Activity: A
Master
R
T
SLAVE
ADDRESS
A
NO
C
DATA
A
K
C
K
DS500070-15
S
T
S
WORD
A
SLAVE
T
ADDRESS
R
ADDRESS
O
T
P
SDA Line
Bus Activity:
EEPROM
A
A
C
C
K
K
A
NO
C
DATA n
A
K
C
K
DS500070-16
Sequential Read (Figure 8)
Bus Activity:
Master
Slave
Address
SDA Line
Bus Activity:
EEPROM
A
C
DATA n +1
K
A
A
A
C
C
C
K
K
K
DATA n +1
DATA n + 2
S
T
O
P
DATA n + x
NO
A
C
K
DS500070-17
NM24C04/05 Rev. G
12
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