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CAT64LC10L-TE13 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part Name
Description
View to exact match
CAT64LC10L-TE13
Catalyst
Catalyst Semiconductor => Onsemi Catalyst
CAT64LC10L-TE13 Datasheet PDF : 12 Pages
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CAT64LC10/20/40
WRITE cycle. The RDY/BSY pin will output the BUSY the device is deselected. The rising edge of the first “1”
status (LOW) one tSV after the rising edge of the 32nd input on the DI pin will reset DO back to the high
clock (the last data bit) and will stay LOW until the write impedance state again.
cycle is complete. Then it will output a logical “1” until the
next WRITE cycle. The RDY/BSY output is not affected
by the input of CS.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
An alternative to get RDY/BSY status is from the DO pin. operation and output a READY status.
During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
NOTE: Data may be corrupted if a RESET occurs while
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed
a WRITE cycle, the DO pin will output a logical “1” when
ts Figure 6. RESET During BUSY Instruction Timing
r RESET
the device is BUSY. If the reset occurs before the BUSY
period, no writing will be initiated. However, if RESET
occurs after the BUSY period, new data will have been
written over the old data.
a SK
P CS
d DI
10100100
ADDRESS*
D15
D0
ue DO
tWR
tin RDY/BUSY
* Please check instruction set table for address
n Figure 7. EWEN Instruction Timing
o RESET
c SK
DisCS
DI
10100011
DO
RDY/BUSY
HIGH-Z
HIGH
5064 FHD F09
Doc. No. 1021, Rev. C
8
 

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