CAT64LC10LA-TE13 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

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CAT64LC10LA-TE13

1K/2K/4K-Bit SPI Serial EEPROM

Catalyst Semiconductor => Onsemi 

CAT64LC10/20/40

a 16-bit data field is also required following the 8-bit Read

address field.

Upon receiving a READ command and address (clocked

The CAT64LC10/20/40 requires an active LOW CS in

order to be selected. Each instruction must be preceded

by a HIGH-to-LOW transition of CS before the input of

the 4-bit start sequence. Prior to the 4-bit start sequence

into the DI pin), the DO pin will output data one tPD after

the falling edge of the 16th clock (the last bit of the

address field). The READ operation is not affected by

the RESET input.

(1010), the device will ignore inputs of all other logical

sequence.

Write

After receiving a WRITE op code, address and data, the

Figure 4. Write Instruction Timing

ts RESET

r SK

Pa CS

device goes into the AUTO-Clear cycle and then the

d DI

10100100

ADDRESS*

D15

D0

e DO

u RDY/BUSY

tin * Please check instruction set table for address

Figure 5. Ready/BUSY Status Instruction Timing

n RESET

LOW

o SK

isc CS

D WRITE INSTRUCTION

NEXT INSTRUCTION

DI

DO

RDY/BUSY

HIGH

7

Doc. No. 1021, Rev. C

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