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IP101A View Datasheet(PDF) - Unspecified

Part Name
Description
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IP101A Datasheet PDF : 36 Pages
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1 Pin Descriptions
Type
LI
I/O
I
O
Description
Latched Input in power up or reset
Bi-directional input and output
Input
Output
IP101A LF
Data Sheet
Type
PD
PU
P
OD
Description
Internal Pull-Down
Internal Pull-Up
Power
Open Drain
Pin no.
Label
Type
Description
MII and PCS Interface - Management Interface Pins
25 MDC
I Management Data Interface Clock: This pin provides a clock
reference to MDIO. The clock rate can be up to 10MHz.
26 MDIO
I/O Management Data interface Input/Output: The function of this
pin is to transfer management information between PHY and
MAC.
MII and PCS Interface – Media Independent Interface (MII) Pins
2
TX_EN
I Transmit Enable: This pin is an active high input. At high status,
(PD) it indicates the nibble data in TXD[3:0] is valid.
7
TX_CLK
O Transmit Clock: This pin provides a continuous 25MHz clock at
100BT and 2.5Mbps at 10BT as timing reference for TXD[3:0]
and TX_EN when the chip operates under MII.
3, 4, 5, 6 TXD[3:0]
I Transmit Data: When TX_EN is set high, MAC will transmit data
through these 4 lines to PHY which the transmission is
synchronizing with TX_CLK.
22 RX_DV
O Receive Data Valid: At high status stands for data flow is
present within RXD[0:3] lines and low means no data exchange
occurred.
16 RX_CLK
O Receive Clock: This pin provides 25MHz for 100BT or 2.5Mhz
for 10BT and RX_DV pin uses this pin as its reference under MII.
18, 19, RXD[3:0]
20, 21
O Receive Data: These 4 data lines are transmission path for PHY
to send data to MAC and they are synchronizing with RX_CLK.
6/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
 

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