ICS853017 View Datasheet(PDF) - Integrated Device Technology

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ICS853017

QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL RECEIVER

Integrated Device Technology 

ICS853017

QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER

APPLICATION INFORMATION

PRELIMINARY

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

DX INPUTS

For applications not requiring the use of a clock input, it can be

left floating. Though not required, but for additional protection, a

1kΩ resistor can be tied from the Dx input to ground.

OUTPUTS:

LVPECL OUTPUTS

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V /2 is

CC

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

CC

and R2/R1 = 0.609.

VCC

Single Ended Clock Input

V_REF

C1

0.1u

R1

1K

PCLK

nPCLK

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER

7

ICS853017AM REV. B OCTOBER 24, 2007

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