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HT66F20 Ver la hoja de datos (PDF) - Holtek Semiconductor

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HT66F20 Enhanced A/D Flash Type MCU 8-Bit MCU with EEPROM Holtek
Holtek Semiconductor Holtek
HT66F20 Datasheet PDF : 246 Pages
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Operating Mode Switching and Wake-up
The device can switch between operating modes dy-
namically allowing the user to select the best perfor-
mance/power ratio for the present task in hand. In this
way microcontroller operations that do not require high
performance can be executed using slower clocks thus
requiring less operating current and prolonging battery
life in portable applications.
In simple terms, Mode Switching between the NORMAL
Mode and SLOW Mode is executed using the HLCLK bit
and CKS2~CKS0 bits in the SMOD register while Mode
Switching from the NORMAL/SLOW Modes to the
SLEEP/IDLE Modes is executed via the HALT instruc-
tion. When a HALT instruction is executed, whether the
device enters the IDLE Mode or the SLEEP Mode is de-
termined by the condition of the IDLEN bit in the SMOD
register and FSYSON in the WDTC register.
When the HLCLK bit switches to a low level, which im-
plies that clock source is switched from the high speed
clock source, fH, to the clock source, fH/2~fH/64 or fL. If
the clock is from the fL, the high speed clock source will
stop running to conserve power. When this happens it
must be noted that the fH/16 and fH/64 internal clock
sources will also stop running, which may affect the op-
eration of other internal functions such as the TMs and
the SIM. The accompanying flowchart shows what hap-
pens when the device moves between the various oper-
ating modes.
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the
high speed system oscillator, and therefore consumes
more power, the system clock can switch to run in the
SLOW Mode by set the HLCLK bit to ²0² and set the
CKS2~CKS0 bits to ²000² or ²001² in the SMOD regis-
ter. This will then use the low speed system oscillator
which will consume less power. Users may decide to do
this for certain operations which do not require high per-
formance and can subsequently reduce power con-
The SLOW Mode is sourced from the LXT or the LIRC
oscillators and therefore requires these oscillators to be
stable before full mode switching occurs. This is moni-
tored using the LTO bit in the SMOD register.
Rev. 1.10
N O R M A L M ode
C K S 2 ~ C K S 0 = 00xB &
H LC LK = 0
S LO W M ode
W D T a n d L V D a r e a ll o ff
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S LE E P 0 M ode
W D T o r L V D is o n
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S LE E P 1 M ode
ID L E N = 1 , F S Y S O N = 0
H A L T in s tr u c tio n is e x e c u te d
ID E L 0 M o d e
ID L E N = 1 , F S Y S O N = 1
H A L T in s tr u c tio n is e x e c u te d
ID L E 1 M o d e
February 1, 2010
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