HT1382 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
View to exact match
HT1382 Datasheet PDF : 29 Pages
| |||
HT1382
I2C/3-Wire Real Time Clock
Acknowledge
Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed
on the bus by the receiver. The master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge (ACK) after the reception of each byte.
The acknowledging device must first pull down the SDA line during the acknowledge clock pulse so
that it remains LOW during the HIGH period of this clock pulse. A master receiver must signal an end
of data to the slave by generating a not-acknowledge (NACK) bit on the last byte that has been clocked
out of the slave. In this case, the master receiver must leave the data line HIGH during the 9th pulse to
not acknowledge. The master will generate a STOP or repeated START condition.
Data Output
By Transmitter
Data Output
By Receiver
SCL from
Master
1
2
S
START
condition
Device Addressing
not acknowledge
acknowledge
7
8
9
clk pulse for
acknowledgement
The slave address byte is the first byte received following the START condition from the master
device. The first seven bits of the first byte make up the slave address. The eighth bit defines a read or
write operation to be performed. When this R/W bit is ²1², then a read operation is selected. A ²0²
selects a write operation. The device address bits are ²1101000². When an address byte is sent, the
device compares the first seven bits after the START condition. If they match, the device outputs an
acknowledge on the SDA line.
MSB
LSB
1 1 0 1 0 0 0 R/W
The first byte after the START.
Write Operation
· Byte Write Operation
A byte write operation requires a START condition, a slave address with R/ bit, a valid Register
Address, the required Data and a STOP condition. After each of the three byte transfers, the device
responds with an ACK.
· Page Write Operation
Following a START condition and slave address, a R/ bit is placed on the bus which indicates to the
addressed device that a Register Address will follow which is to be written to the address pointer.
The data to be written to the memory follows next and the internal address pointer is incremented to
the next address location on the reception of an acknowledge clock. After reaching memory location
0Fh, the pointer will be reset to 00h.
Slave Address
Register Address(An)
Data(n)
S1 1 0 1 0 0 0 0
P
Write
ACK
ACK
ACK
Byte Write Sequence
Rev. 1.40
17
May 27, 2011
|
|
Share Link: 