HT1382 View Datasheet(PDF) - Holtek Semiconductor

Part Name

Description

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HT1382

I2C/3-Wire Real Time Clock

Holtek Semiconductor 

HT1382

I2C/3-Wire Real Time Clock

Interrupt Mode Enable Bit - IME

This bit enables/disables the interrupt mode of the alarm function. When the IME bit is set to ²1², the

interrupt mode is enabled and when the IME bit is cleared to ²0², the interrupt mode is disabled and the

alarm operates in single mode.

Alarm Register

The addresses of alarm registers are 0Bh to 10h. The data is stored in the BCD format. The MSB of

each alarm register is an enable bit. (enable=²1²). These enable bits specify which alarm registers are

used to make the comparison between the alarm registers and the RTC registers. There is no alarm byte

for year. When a compare match condition exists, the AI bit is set to ²1², and the IRQ pin is activated.

To clear an alarm, the AI bit must be cleared to ²0². If the ARE bit is set to ²1², the AI bit will

automatically be cleared when the status register is read.

There are two alarm operation modes: Single mode and Interrupt Mode.

Single mode: set the AE bit to ²1², the IME bit to ²0², and disable the frequency output. When the RTC

register values match the alarm registers values, the AI bit will be set to ²1² and the alarm condition

activates the IRQ pin. The IRQ pin will remain low until the AI bit is cleared to ²0².

Interrupt mode: set the AE bit to ²1², the IME bit to ²1², and disable the frequency output. When the

RTC registers values match the alarm registers values, the IRQ pin will be pulled low for 250ms and

the AI bit will be set to ²1². This mode allows for a repetitive or recurring alarm function. When the

alarm is set, the device will continue to activate an alarm for each match of the alarm and the present

time. For example, if only the seconds are set, it will activate an alarm every minute, if only the

minutes are set, it will activate an alarm every hour.

EEPROM User Data

The HT1382 provides 4 bytes EEPROM for user. The EEPROM will continue to operate in battery

backup mode. However, it should be noted that the I2C/3-wire interface is disabled in battery backup

mode. User must detect the status of EB bit before reading data or writing data. If the EB bit is ²0², it is

valid to read data or write data. If the EB bit is ²1², it is invalid to read data or write data.

Rev. 1.40

15

May 27, 2011

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