HM5259165B-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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HM5259165B-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5259165B/HM5259805B/HM5259405B-75/A6

Refresh

Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto-

refresh command updates the internal counter every time it is executed and determines the banks and the

ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 8192

cycles/32 ms. (8192 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-

Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the

auto-refresh, an additional precharge operation by the precharge command is not required.

Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held

Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-

refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh

to all refresh addresses in or within 32 ms period on the condition (1) and (2) below.

(1) Enter self-refresh mode within 3.9 µs after either burst refresh or distributed refresh at equal interval to all

refresh addresses are completed.

(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 3.9 µs after exiting

from self-refresh mode.

Others

Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In

power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down

mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the

power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not

performed.

Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM

enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal

state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command

input is enabled from the next clock. For details, refer to the "CKE Truth Table".

Power-up sequence: The SDRAM should be goes on the following sequence with power up.

The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes.

The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.

The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization

sequence.

This SDRAM has VCC clamp diodes for CLK, CKE, CS DQM, DQMU/DQML and DQ pins. If these pins go

high before power up, the large current flows from these pins to VCC through the diodes.

Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must be

precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands

(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by

keeping DQM, DQMU/DQML and CKE to High, the output buffer becomes High-Z during Initialization

sequence, to avoid DQ bus contention on memory system formed with a number of device.

Data Sheet E0118H10

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