datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

HM5259165B-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name
Description
View to exact match
HM5259165B-75 Datasheet PDF : 63 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
HM5259165B/HM5259805B/HM5259405B-75/A6
DQM Control
The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data,
respectively. The timing of DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting
DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM,
DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.
However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2
clocks.
Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low,
data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not
written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.
Reading
CLK
DQM,
DQMU/DQML
DQ (output)
Writing
CLK
DQM,
DQMU/DQML
DQ (input)
out 0
out 1
High-Z
out 3
lDOD = 2 Latency
in 0
;;;in 1
in 3
lDID = 0 Latency
Data Sheet E0118H10
39
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]