HM5259165B-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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HM5259165B-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5259165B/HM5259805B/HM5259405B-75/A6

Write command to Precharge command interval (same bank): When the precharge command is executed

for the same bank as the write command that preceded it, the minimum interval between the two commands is

1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of

DQM, DQMU/DQML for assurance of the clock defined by tDPL.

WRITE to PRECHARGE Command Interval (same bank)

Burst Length = 4 (To stop write operation)

CLK

Command

DQM,

DQMU/DQML

Din

CLK

Command

DQM,

DQMU/DQML

Din

WRIT PRE/PALL

tDPL

WRIT

PRE/PALL

in A0

in A1

tDPL

Burst Length = 4 (To write all data)

CLK

Command

DQM,

DQMU/DQML

Din

WRIT

PRE/PALL

in A0

in A1

in A2

in A3

tDPL

Data Sheet E0118H10

36

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