HM5259165B-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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HM5259165B-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5259165B/HM5259805B/HM5259405B-75/A6

Write with auto-precharge: In this operation, since precharge is automatically performed after completing

a burst write or single write operation, a precharge command need not be executed after each write operation.

The command executed for the same bank after the execution of this command must be the bank active

(ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of

next command.

Burst Write (Burst Length = 4)

CLK

Command ACTV

WRIT A

IRAS

ACTV

DQ (input)

in0 in1 in2 in3

lAPW

Note: Internal auto-precharge starts at the timing indicated by " ".

and an interval of tRAS (lRAS) is required between previous active (ACTV) command

and internal precharge " ".

Single Write

CLK

Command ACTV

WRIT A

IRAS

ACTV

DQ (input)

in

lAPW

Note: Internal auto-precharge starts at the timing indicated by " ".

and an interval of tRAS (lRAS) is required between previous active (ACTV) command

and internal precharge " ".

Data Sheet E0118H10

26

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