HM5259165B-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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HM5259165B-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5259165B/HM5259805B/HM5259405B-75/A6

Mode Register Configuration

The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set

cycles. The mode register consists of five sections, each of which is assigned to address pins.

BA1, BA0, A11, A10, A12, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the

burst write mode, and the other is the single write mode. These bits specify write mode.

Burst read and burst write: Burst write is performed for the specified burst length starting from the column

address specified in the write cycle.

Burst read and single write: Data is only written to the column address specified during the write cycle,

regardless of the burst length.

A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.

A6, A5, A4: (LMODE): These pins specify the CAS latency.

A3: (BT): A burst type is specified.

A2, A1, A0: (BL): These pins specify the burst length.

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

OPCODE

0

LMODE

BT

BL

A6 A5 A4 CAS latency

00 0

R

A3 Burst type

0 Sequential

Burst length

A2 A1 A0

BT=0 BT=1

00 1

R

1 Interleave

00 0 1

1

01 0

2

00 1 2

2

01 1

3

01 0 4

4

1XX

R

01 1 8

8

10 0 R

R

BA1 BA0 A12 A11 A10 A9

0 00 0 00

X XX X X0

A8 Write mode

0 Burst read and burst write

1

R

10 1 R

R

11 0 R

R

11 1 R

R

X XX X

X XX X

X1

X1

0 Burst read and single write

1

R

R is Reserved (inhibit)

X: 0 or 1

Data Sheet E0118H10

20

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