HM5259165B-75 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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HM5259165B-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5259165B/HM5259805B/HM5259405B-75/A6

DQM Truth Table (HM5259165B)

Command

Symbol

Upper byte (DQ8 to DQ15) write enable/output enable ENBU

Lower byte (DQ0 to DQ7) write enable/output enable ENBL

Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU

Lower byte (DQ0 to DQ7) write inhibit/output disable MASKL

Note:

H: VIH. L: VIL. ×: VIH or VIL.

Write: IDID is needed.

Read: IDOD is needed.

DQM Truth Table (HM5259805B/HM5259405B)

CKE

n-1

H

H

H

H

Command

Write enable/output enable

Write inhibit/output disable

Note:

H: VIH. L: VIL. ×: VIH or VIL.

Write: IDID is needed.

Read: IDOD is needed.

Symbol

ENB

MASK

CKE

n-1

H

H

n

×

×

×

×

n

×

×

DQMU

L

×

H

×

DQML

×

L

×

H

DQM

L

H

The SDRAM can mask input/output data by means of DQM, DQMU/DQML.

DQMU masks the upper byte and DQML masks the lower byte. (HM5259165B)

During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data

output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,

disabling data output.

During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set

to High, the previous data is held (the new data is not written). Desired data can be masked during burst read

or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the

SDRAM operating instructions.

Data Sheet E0118H10

12

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