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ICL232CBEZ View Datasheet(PDF) - Intersil

Part NameICL232CBEZ Intersil
Intersil Intersil
Description+5V powered, dual RS-232 transmitter/receiver
ICL232CBEZ Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
ICL232
Pin Descriptions (Continued)
PDIP, CERDIP
SOIC
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
PIN NAME
R2out
T2IN
T1IN
R1OUT
R1IN
T1OUT
GND
VCC
DESCRIPTION
Receiver 2 TTL/CMOS output.
Transmitter 2 TTL/CMOS input, with internal 400K pullup resistor to VCC.
Transmitter 1 TTL/CMOS input, with internal 400K pullup resistor to VCC.
Receiver 1 TTL/CMOS output.
RS-232 Receiver 1 input, with internal 5K pulldown resistor to GND.
RS-232 Transmitter 1 output ±10V (typical).
Supply Ground.
Positive Power Supply +5V ±10%
VCC
GND
VOLTAGE DOUBLER
S1
C1+
S2
+
- C1
S3
C1-
S4
V+ = 2VCC
VOLTAGE INVERTER
S5
C2+
S6
+
- C3
VCC
GND
S7
+
- C2
C2-
S8
+
- C4
GND
V- = -(V+)
RC
OSCILLATOR
FIGURE 5. DUAL CHARGE PUMP
Detailed Description
The ICL232 is a dual RS-232 transmitter/receiver powered by
a single +5V power supply which meets all ElA RS232C
specifications and features low power consumption. The
functional diagram illustrates the major elements of the
ICL232. The circuit is divided into three sections: a voltage
doubler/inverter, dual transmitters, and dual receivers Voltage
Converter.
An equivalent circuit of the dual charge pump is illustrated in
Figure 5.
The voltage quadrupler contains two charge pumps which use
two phases of an internally generated clock to generate +10V
and -10V. The nominal clock frequency is 16kHz. During
phase one of the clock, capacitor C1 is charged to VCC.
During phase two, the voltage on C1 is added to VCC,
producing a signal across C2 equal to twice VCC. At the same
time, C3 is also charged to 2VCC, and then during phase one,
it is inverted with respect to ground to produce a signal across
C4 equal to -2VCC. The voltage converter accepts input
voltages up to 5.5V. The output impedance of the doubler (V+)
is approximately 200, and the output impedance of the
inverter (V-) is approximately 450. Typical graphs are
presented which show the voltage converters output vs input
voltage and output voltages vs load characteristics. The test
circuit (Figure 3) uses 1µF capacitors for C1-C4, however, the
value is not critical. Increasing the values of C1 and C2 will
lower the output impedance of the voltage doubler and
inverter, and increasing the values of the reservoir capacitors,
C3 and C4, lowers the ripple on the V+ and V- supplies.
T1IN, T2IN
T1OUT, T2OUT
90%
10%
tf
tr
VOH
VOL
Instantaneous
Slew Rate (SR)
=
(0.8)
(VOH
tr
-
VOL)
or
(0.8)
(VOL
tf
-
VOH)
FIGURE 6. SLEW RATE DEFINITION
Transmitters
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic
threshold is about 26% of VCC , or 1.3V for VCC = 5V. A logic
1 at the input results in a voltage of between -5V and V- at the
output, and a logic 0 results in a voltage between +5V and (V+
- 0.6V). Each transmitter input has an internal 400kpullup
resistor so any unused input can be left unconnected and its
output remains in its low state. The output voltage swing
meets the RS-232C specification of ±5V minimum with the
worst case conditions of: both transmitters driving 3k
minimum load impedance, VCC = 4.5V, and maximum
allowable operating temperature. The transmitters have an
internally limited output slew rate which is less than 30V/µs.
The outputs are short circuit protected and can be shorted to
ground indefinitely. The powered down output impedance is a
5
FN3020.7
July 28, 2005
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The ICL232 is a dual RS-232 transmitter/receiver interface circuit that meets all ElA RS-232C and V.28 specifications. It requires a single +5V power supply, and features two onboard charge pump voltage converters which generate +10V and -10V supplies from the 5V supply. The drivers feature true TTL/CMOS input compatibility, slew rate-limited output, and 300Ωpower-off source impedance. The receivers can handle up to +30V, and have a 3kΩ to 7kΩinput impedance. The receivers also have hysteresis to improve noise rejection.

 

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