HI-8581PJI-10 View Datasheet(PDF) - Holt Integrated Circuits
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HI-8581PJI-10 Datasheet PDF : 15 Pages
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HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing each receiver’s logic.
BIT TIMING
ARINC 429 specifies the following timing for received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 - 41.7 µsec
The HI-8581 and HI-8589 accepts signals meeting these specifi-
cations and rejects signals outside these tolerances using the
method described here:
1. The timing logic requires an accurate 1.0 MHz clock
source. Less than 0.1% error is recommended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. To qualify data bits, One or Zero in the upper
bits of the sampling shift register must be followed by Null in
the lower bits within the data bit time. A word gap Null re-
quires three consecutive Nulls in both the upper and lower
bits of the sampling shift register. This guarantees the mini-
mum pulse width.
3. Each data bit must follow its predecessor by not less than
8 samples and not more than 12 samples. In this manner the
bit rate is checked. With exactly 1 MHz input clock frequency,
the acceptable data bit rates are as follows:
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 enables the next reception.
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is re-
ceived from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will al-
ways be a “0” when valid (odd parity) ARINC 429 words are re-
ceived.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver remains low until after both ARINC bytes
from that receiver are retrieved. This is accomplished by first acti-
vating EN with SEL, the byte selector, low to retrieve the first byte
and then activating EN with SEL high to retrieve the second byte.
EN1 retrieves data from receiver 1 and EN2 retrieves data from re-
ceiver 2.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
SEL
EN
D/R
DECODER
CONTROL
BITS
MUX
CONTROL
/
LATCH
ENABLE
CONTROL
BITS 9 & 10
EOS
TO PINS
32 TO 16 DRIVER
CONTROL
BIT BD14
CLOCK
OPTION
32 BIT LATCH
32 BIT SHIFT REGISTER
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
EOS
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
START
SEQUENCE
CONTROL
BIT CLOCK
END
CLOCK
CLK
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
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