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HCNW2211-300 View Datasheet(PDF) - Avago Technologies

Part NameDescriptionManufacturer
HCNW2211-300 Very High CMR, Wide VCC Logic Gate Optocouplers AVAGO
Avago Technologies AVAGO
HCNW2211-300 Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
VCC1 (+5 V)
DATA INPUT
80 Ω
1.1 kΩ
HCPL-2201/11
HCPL-02XX
HCNW22XX
1
120 pF
2
3
TTL OR LSTTL
4
8
7
6*
5
1
* 0.1 µF BYPASS
VCC2 (+5 V)
DATA OUTPUT
UP TO 16 LSTTL LOADS
OR 4 TTL LOADS
2
Figure 13b. Recommended LSTTL to LSTTL circuit for applications requiring a maximum allowable propagation delay of 300 ns.
VCC1 (+5 V)
DATA INPUT
80 Ω*
1.1 kΩ
HCPL-2201 fig 13b
HCPL-2201/11
HCPL-02XX
HCNW22XX
VCC2
(4.5 TO 20 V)
1
120 pF*
2
VCC 8
7
RL
CMOS
DATA OUTPUT
3
TTL OR LSTTL
4
6
**
GND 5
TOTEM
POLE
OUTPUT
1
GATE
VCC2
5V
10 V
15 V
20 V
RL
1.1 kΩ
2.37 kΩ
3.83 kΩ
5.11 kΩ
2
* 120 pF PEAKING CAPACITOR
MAY BE OMITTED AND 80 Ω
RESISTOR MAY BE SHORTED
WHERE 500 ns PROPAGATION
DELAY IS SUFFICIENT.
**0.1 µF BYPASS
VCC1 (+5 V)
DATA
INPUT
TTL or
LSTTL
1.1 kΩ
D1
HCPL-2201/11
HCPL-02XX
HCNW22XX
1
VCC 8
2
7
3
6
4
GND 5
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
Figure 14. LSTTL to CMOS interface circuit.
VCC (+5 V)
DATA INPUT
HCPL-2201 fig 14
80 Ω*
1.1 kΩ
1
120 pF*
2
4.7 kΩ
3
TTL OR LSTTL
4
HCPL-2201/11
HCPL-02XX
HCNW22XX
VCC 8
7
6
GND 5
OPEN
COLLECTOR
GATE
* 120 pF PEAKING CAPACITOR
MAY BE OMITTED AND 80 Ω
RESISTOR MAY BE SHORTED
WHERE 500 ns PROPAGATION
DELAY IS SUFFICIENT.
Figure 15. Alternative LED drive circuit.
HCPL-2201 fig 15
Figure 16. Series LED drive with open collector gate (4.7 k resistor shunts IOH from the LED).
17
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