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HCPL-050L View Datasheet(PDF) - Avago Technologies

Part NameHCPL-050L AVAGO
Avago Technologies AVAGO
DescriptionLVTTL/LVCMOS Compatible 3.3 V Optocouplers (1 Mb/s)
HCPL-050L Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Package Characteristics
Over Recommended Temperature (TA = 0˚C to 70˚C) unless otherwise specified.
Parameter
Sym. Device
Min. Typ.* Max. Units
Input-Output VISO
Momentary
8-Pin DIP
3750
V rms
SO-8
Withstand
Voltage**
II-O
8-Pin DIP
1
µA
Input-Output RI-O 8-Pin DIP
1012
Resistance
SO-8
Input-Output CI-O 8-Pin DIP
0.6
pF
Capacitance
SO-8
Test Conditions
Fig.
RH < 50%,
t = 1 min.,
TA = 25˚C
45% RH, t = 5 s,
VI-O = 3 kVdc,
TA = 25˚C
VI-O = 500 Vdc
f = 1 MHz
Note
6, 14
6, 16
6
6
*All typicals at TA = 25˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable),
your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage," publica-
tion number 5963-2203E.
Notes:
1. Derate linearly above 70˚C free-air temperature at a rate of 0.8 mA/˚C (8-Pin DIP).
Derate linearly above 85˚C free-air temperature at a rate of 0.5 mA/˚C (SO-8).
2. Derate linearly above 70˚C free-air temperature at a rate of 1.6 mA/˚C (8-Pin DIP).
Derate linearly above 85˚C free-air temperature at a rate of 1.0 mA/˚C (SO-8).
3. Derate linearly above 70˚C free-air temperature at a rate of 0.9 mW/˚C (8-Pin DIP).
Derate linearly above 85˚C free-air temperature at a rate of 1.1 mW/˚C (SO-8).
4. Derate linearly above 70˚C free-air temperature at a rate of 2.0 mW/˚C (8-Pin DIP).
Derate linearly above 85˚C free-air temperature at a rate of 2.3 mW/˚C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the leading edge of the com-
mon mode pulse signal, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient im-
munity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to
assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 mA kΩ pull-up resistor.
9. The 4.1 kΩ load represents 1 LSTTL unit load of 0.36 mA and 6.1 kΩ pull-up resistor.
10. The frequency at which the AC output voltage is 3 dB below its mid-frequency value.
11. The JEDEC registration for the 6N136 specifies a minimum CTR of 15%. Avago guarantees a minimum CTR of 15%.
12. See Option 020 data sheet for more information.
13. Use of a 0.1 µf bypass capacitor connected between pins 5 and 8 is recommended.
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-2 Insula-
tion Related Characteristics Table, if applicable.
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-2 Insula-
tion Related Characteristics Table, if applicable.
16. This rating is equally validated by an equivalent AC proof test.
10
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Description
These diode-transistor optocouplers use an insulating layer between a LED and an integrated photodetector to provide electrical insulation between input and output. Separate connections for the photodiode bias and output transistor collector increase the speed up to a hundred times that of a conventional phototransistor coupler by reducing the base collector capacitance.

Features
• 3.3V/5V Dual Supply Voltages
• Low power consumption
• High speed: 1 Mb/s
• LVTTL/LVCMOS compatible
• Available in 8-pin DIP, SO-8
• Open collector output
• Guaranteed performance from temperature: 0˚C to +70˚C
• Safety approval, UL, CSA, IEC/EN/DIN EN 60747-5-2

Applications
• High voltage insulation
• Video signal isolation
• Power translator isolation in motor drives
• Line receivers
• Feedback element in switched mode power supplies
• High speed logic ground isolation – LVTTL/LVCMOS
• Replaces pulse transformers
• Replaces slow phototransistor isolators

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