AD261BND-0 View Datasheet(PDF) - Analog Devices
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Description
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AD261BND-0 Datasheet PDF : 7 Pages
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AD261
Logic information is sent across the barrier as “set-hi/set-lo”
data that is derived from logic level transitions of the input. At
power-up or after a fault condition, an output might not repre-
sent the state of the respective channel input to the isolator. An
internal circuit operates in the background which interrogates
all inputs about every 5 µs and in the absence of logic transi-
tions, sends appropriate “set-hi” or “set-lo” data across the
barrier.
Recovery time from a fault condition or at power-up is thus
between 5 µs and 10 µs.
INPUT
SCHMITT
TRIGGER
BUFFER
3.5kV
ISOLATION DATA OUTPUT
DRIVER BARRIER RECEIVER BUFFER
DATA IN
DQ
OUT
ENABLE
G
GATED
TRANSPARENT
LATCH
CONTINUOUS
UPDATE CIRCUIT
Figure 1. Simplified Block Diagram
ENABLE
POSITIVE GOING
INPUT THRESHOLD
NEGATIVE GOING
INPUT THRESHOLD
HYSTERESIS
OUTPUT
63%
tff
PROPAGATION DELAY
tPD = 14ns
37%
EFFECTIVE
CIRCUIT
MODEL
5pF
INPUT
CAPACITANCE
BUFFER
DELAY LINE
BUFFER
14ns
100⍀
trr = tff = 100⍀ x CTOTAL OUTPUT CAPACITANCE
Х0.5ns – NO LOAD
5pF
OUTPUT
CAPACITANCE
= 5.5ns INTO 50pF
TOTAL DELAY = tPD ؉ trr = 13ns (NO LOAD), 18ns (50pF LOAD)
Figure 2. Typical Timing and Delay Models
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
22-Pin Plastic DIP
(ND-22A)
1.500 (38.1) MAX
0.550 (13.97)
MAX
0.440
SIDE VIEW
(11.18) END VIEW
1
8
MAX
15
22
0.160 (4.06) 0.050 (1.27)
0.140 (3.56)
0.075 (1.91)
PIN 1
0.020 ؋ 0.010
(0.508 ؋ 0.254)
16 PLACES
0.100
(2.54)
0.250
(6.35)
SYSTEM
BOTTOM
VIEW
0.738* (18.75)
FIELD
0.650 (16.51)
0.050
(1.27)
*CREEPAGE PATH (SUBTRACT APPROXIMATELY
0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD.
THIS SPACING SUPPORTS THE INTRINSICALLY SAFE
RATING OF 750V.
0.350
(8.89)
–6–
REV. 0
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