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GS1540 View Datasheet(PDF) - Gennum -> Semtech

Part Name
Description
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GS1540 Datasheet PDF : 17 Pages
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PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
72
LFA_VCC
73
LFA
74
LBCONT
75
LFA_VEE
76
DFT_VEE
79, 80
81, 85
86
89
91
DM, DM
LFS, LFS
IJI
VCO
VCO
93, 96
98
PLCAP, PLCAP
PLL_LOCK
105
BYPASS
106
108, 109
110
112
113
DDI_VTT
DDI, DDI
PD_VCC
PDSUB_VEE
PD_VEE
LEVEL
Power
Analog
Analog
Power
Power
Analog
Analog
Analog
Analog
Analog
Analog
TTL
TTL
Analog
Differential
ECL/PECL
Power
Power
Power
TYPE
DESCRIPTION
Input Positive Supply. Loop filter most positive power supply connection.
Output Control Signal Output. Control voltage for GO1515 VCO.
Input Control Signal Input. Used to provide electronic control of Loop
Bandwidth.
Input Negative Supply. Loop filter most negative power supply connection.
Input
Most negative power supply connection - enables the jitter
demodulator functionality. This pin should be connected to ground. If
left floating, the DM function is disabled resulting in a current saving of
340µA.
Output Test Signal. Used for manufacturing test only.
These pins must be floating for normal operation.
Input Loop Filter Connections.
Output Status Signal Output. Approximates the amount of excessive jitter on
the incoming DDI and DDI input.
Input Control Signal Input. Input pin is AC coupled to ground using a 50
transmission line.
Input
Control Signal Input. Voltage controlled oscillator input. This pin is
connected to the output pin of the GO1515 VCO.
This pin must be connected to the GO1515 VCO output pin via a 50
transmission line.
Input Control Signal Input. Phase lock detect time constant capacitor.
Output
Status Indicator Signal. This signal is a combination (logical AND) of
the carrier detect and phase lock signals.
When input is present and PLL is locked, the PLL_LOCK goes high
and the outputs are valid. When the PLL_LOCK output is low the data
output is muted (latched at the last state).
PLL_LOCK is independent of the BYPASS signal.
Input
Control Signal Input. Selectable input that controls whether the input
signal is reclocked or passed through the chip.
When BYPASS is high; the input signal is reclocked.
When BYPASS is low; the input signal is passed through the chip and
not reclocked. Muting does not effect bypassed signal.
Input
Bias Input. Selectable input for interfacing standard ECL outputs
requiring 50pull down to VTT power supply for a seamless interface.
See Typical Application Circuit for recommended circuit application.
Input
Digital Data Input Signals. Digital input signals from a GS1504
Equalizer or HD crosspoint switch.
Because of on chip 50termination resistors, a PCB trace
characteristic impedance of 50is recommended.
Positive Supply. Phase detector most positive power supply
connection.
Input Substrate Connection. Connect to phase detector’s most negative
power supply.
Input Negative Supply. Phase detector most negative power supply
connection.
GENNUM CORPORATION
8 of 17
522 - 27 - 03
 

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