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GMS82524TK View Datasheet(PDF) - Hynix Semiconductor

Part Name
Description
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GMS82524TK
Hynix
Hynix Semiconductor Hynix
GMS82524TK Datasheet PDF : 93 Pages
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GMS82512/16/24
HYUNDAI MicroElectronics
.
INT0
INT1
INT2
INT3
Timer 0
Timer 1
Timer 2
Timer 3
A/D Converter
Watchdog Timer
BIT
Internal bus line
IRQH
[0F7H]
INT0IF
INT1IF
INT2IF
INT3IF
T0IF
T1IF
T2IF
T3IF
IRQL
[0F5H]
ADIF
WDTIF
BITIF
[0F6H]
IENH
Interrupt Enable
Register (Higher byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP
I-flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
[0F4H]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 14-2 Block Diagram of Interrupt
R/W
IENH INT0E
MSB
R/W R/W R/W
INT1E INT2E INT3E
R/W
T0E
R/W R/W
T1E T2E
R/W
T3E
LSB
ADDRESS: 0F6H
INITIAL VALUE: 0000 0000B
Timer/Counter 3 interrupt enable flag
Timer/Counter 2 interrupt enable flag
Timer/Counter 1 interrupt enable flag
Timer/Counter 0 interrupt enable flag
External interrupt 3 enable flag
External interrupt 2 enable flag
External interrupt 1 enable flag
External interrupt 0 enable flag
R/W R/W R/W
IENL
ADE WDTE BITE
-
-
-
-
-
ADDRESS: 0F4H
INITIAL VALUE: 000- ----B
MSB
LSB
Basic Interval Timer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Converter interrupt enable flag
VALUE
0: Disable
1: Enable
Figure 14-3 Interrupt Enable Flag
48
FEB. 2000 Ver 1.00
 

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