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Q0565R_07-2007 Просмотр технического описания (PDF) - Fairchild Semiconductor

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Q0565R_07(2007) Green-Mode Fairchild Power Switch (FPS?) for Quasi-Resonant Operation - Low EMI and High Efficiency Fairchild
Fairchild Semiconductor Fairchild
Q0565R_07 Datasheet PDF : 22 Pages
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Functional Description
1. Start-up: At start-up, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (Ca) connected to the VCC pin, as
illustrated in Figure 22. When VCC reaches 12V, the
FPS™ begins switching and the internal high-voltage
current source is disabled. The FPS continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless VCC goes below the
stop voltage of 8V.
VDC
Ca
VCC
3
6 Vstr
8V/12V
FSQ0765R Rev.00
VCC good
ICH
Vref
Internal
Bias
Figure 22. Start-up Circuit
2. Feedback Control: FPS employs current-mode
control, as shown in Figure 23. An opto-coupler (such as
the FOD817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the Rsense resistor makes it possible to control the
switching duty cycle. When the reference pin voltage of
the shunt regulator exceeds the internal reference
voltage of 2.5V, the opto-coupler LED current increases,
pulling down the feedback voltage and reducing the duty
cycle. This typically happens when the input voltage is
increased or the output load is decreased.
2.1 Pulse-by-Pulse Current Limit: Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (VFB*), as shown in Figure 23. Assuming
that the 0.9mA current source flows only through the
internal resistor (3R + R = 2.8k), the cathode voltage of
diode D2 is about 2.5V. Since D1 is blocked when the
feedback voltage (VFB) exceeds 2.5V, the maximum
voltage of the cathode of D2 is clamped at this voltage,
clamping VFB*. Therefore, the peak value of the current
through the SenseFET is limited.
2.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the Rsense
resistor would lead to incorrect feedback operation in the
current-mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(tLEB) after the SenseFET is turned on.
VCC
Idelay
Vref
IFB
VO
VFB
4
OSC
FOD817A
D1 D2
CB
3R
KA431
+
VFB* R
-
SenseFET
Gate
driver
FSQ0765R Rev. 00
VSD
OLP
Rsense
Figure 23. Pulse-Width-Modulation (PWM) Circuit
3. Synchronization: The FSQ-series employs a quasi-
resonant switching technique to minimize the switching
noise and loss. The basic waveforms of the quasi-
resonant converter are shown in Figure 24. To minimize
the MOSFET's switching loss, the MOSFET should be
turned on when the drain voltage reaches its minimum
value, which is indirectly detected by monitoring the VCC
winding voltage, as shown in Figure 24.
Vds
VDC
VRO
VRO
Vsync
tF
Vovp (8V)
1.2V
MOSFET Gate
1.0V
230ns Delay
ON
ON
FSQ0765R Rev.00
Figure 24. Quasi-Resonant Switching Waveforms
© 2007 Fairchild Semiconductor Corporation
FSQ0565R, FSQ0765R Rev. 1.0.0
12
www.fairchildsemi.com
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