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FOD3182 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
FOD3182 Datasheet PDF : 23 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Package Dimensions
Through Hole
9.40–9.91
Pin 1
6.35–6.86
3.68–3.94
5.08
MAX
0.51 MIN
0.41–0.56
2.54 BSC
1.14–1.78
3.05–3.90
(0.78)
0.20–0.40
7.62 TYP
0.4" Lead Spacing (Option T)
9.40–9.91
Pin 1
6.35–6.86
3.68–3.94
5.08
MAX
0.51 MIN
0.41–0.56
2.54 BSC
1.14–1.78
3.05–3.90
(0.78)
15.0° MAX
10.16 TYP
0.20–0.40
Surface Mount – 0.3" Lead Spacing (Option S)
9.40–9.91
Pin 1
(1.78)
(2.54)
6.35–6.86
(7.49)
(10.54)
(1.54)
3.68–3.94
5.08
MAX
1.14–1.78
(0.76)
Recommended Land Pattern
(Option S)
0.20–0.40
0.51 MIN
2.54 BSC
(0.78)
(0.41–0.56)
0.40 MIN
Both sides
8.00 MIN
10.30 MAX
Note:
1. All dimensions are in millimeters.
2. Dimensions are exclusive of burrs, mold fash, and tie bar extrusion.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2010 Fairchild Semiconductor Corporation
FOD3182 Rev. 1.0.9
17
www.fairchildsemi.com
 

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