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CX06832-15 View Datasheet(PDF) - Conexant Systems

Part NameDescriptionManufacturer
CX06832-15 V.34/Group 3 High Performance Fax Modem Family Conexant
Conexant Systems Conexant
CX06832-15 Datasheet PDF : 15 Pages
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V.34/Group 3 High Performance Fax Modem Family
FM336Plus
Data Formats
Serial Synchronous Data
Data rate: 300–56000 bps (-D90) or
300–33600 bps ±0.01%
Selectable clock: Internal, external, or slave
Serial Asynchronous Data (-D / -D90)
Data rate: 300–56000 bps (-D90) or
300–33600 bps +1%/–2.5% or +2.3%/–2.5%; up to
300 bps (V.21 and Bell 103); 1200/75 bps (V.23)
Data bits per character: 7, 8, 9, 10, or 11
Parallel Synchronous Data
Normal sync: 8-bit data for transmit and receive
Data rate: 300–56000 bps (-D90) or
300–33600 bps ±0.01%
SDLC/HDLC support:
Transmitter: Flag generation, 0-bit stuffing,
CRC-16 or CRC-32 generation
Receiver: Flag detection, 0-bit deletion, CRC-16
or CRC-32 checking
Parallel Asynchronous Data (-D / -D90)
Data rate: 300–56000 bps (-D90) or
300–33600 bps +1%/–2.5% or +2.3%/–2.5%;
1200, 300, or 75 bps (FSK)
Data bits per character: 5, 6, 7, or 8
Parity generation/checking: Odd, Even,
or 9th data bit
Async/Sync and Sync/Async Conversion
(-D / -D90)
An asynchronous-to-synchronous converter is provided
in the transmitter and a synchronous-to-asynchronous
converter is provided in the receiver. The converters
operate in both serial and parallel modes. The
asynchronous character format is 1 start bit, 5 to 8
data bits, an optional parity bit, and 1 or 2 stop bits.
Valid character size, including all bits, is 7, 8, 9, 10, or
11 bits per character. Two ranges of signaling rates
are provided:
Basic range: +1% to –2.5%
Extended overspeed range: +2.3% to –2.5%
When the transmit converter is operating at the basic
signaling rate, no more than one stop bit will be deleted
per eight consecutive characters. When operating at
the extended rate, no more than one stop bit will be
deleted per four consecutive characters. Break
handling is performed as described in V.14.
Asynchronous characters are accepted on the TXD
serial input and are issued on the RXD serial output.
V.54 Inter-DCE Signaling (-D / -D90)
The modem supports V.54 inter-DCE signaling
procedures in synchronous and asynchronous
configurations. Transmission and detection of the
preparatory, acknowledgment, and termination phases
as defined in V.54 are provided. Three control bits
(V54T, V54A, and V54P) in the transmitter allow the
host to send the appropriate bit patterns. Three control
bits (V54TE, V54AE, and V54PE) in the receiver are
used to enable one of three bit pattern detectors. A
status bit (V54DT) indicates when the selected pattern
detector has found the corresponding bit pattern.
V.13 Remote RTS Signaling (-D / -D90)
The modem supports V.13 remote RTS signaling.
Transmission and detection of signaling bit patterns in
response to a change of state in the RTS bit or the
/RTS input signal are provided. This feature may be
used to clamp/unclamp the local /RLSD and RXD
signals in response to a change in the remote /RTS
signal in order to simulate controlled carrier operation
in a constant carrier environment. The modem
automatically clamps and unclamps /RLSD.
In-Band Secondary Channel (-D / -D90)
A duplex in-band secondary channel is provided in
V.34 (all speeds) and V.32 bis/V.32 (7200 bps and
above) modes. The secondary channel operates in
parallel data mode with independent transmit and
receive interrupts and data buffers. The main channel
may operate in parallel or serial mode.
In V.34 modes, the secondary channel rate is 200 bps.
In V.32 bis/V.32 modes, the secondary channel rate
is 150 bps. This rate is also host programmable in
V.32 bis/V.32 modes.
Transmit and Receive FIFO Data Buffers
Two 16-byte first-in first-out (FIFO) data buffers allow
the DTE/host to output up to 16 bytes of transmit data
to the transmitter FIFO (TXFIFO) and input up to
16 bytes of accumulated received data from the
receiver FIFO (RXFIFO). The TXFIFO and RXFIFO
can be extended up to 255 bytes. The size of the FIFO
extension is 255 bytes overall and can be divided
between the two FIFOs in any proportion.
The RXFIFO is always enabled. The host can enable
the TXFIFO. Status bits indicate when the TXFIFO is
not full, the TXFIFO is half-full (eight or more bytes
loaded), the RXFIFO is empty, and the RXFIFO is half-
full. An interrupt mask register allows an interrupt
request to be generated whenever the status bits
change state.
101361A
Conexant
6
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