FIN3386 View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

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FIN3386

Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer

Fairchild Semiconductor 

AC Loadings and Waveforms (Continued)

Figure 23. Transmitter Clock Out Jitter Measurement Setup

Note:

25. Test setup considers no requirement for separation of RMS and deterministic jitter. Other hardware setups,

such as Wavecrest boxes, can be used if no M1 software is available, but the test methodology in Figure 24

should be followed.

Figure 24. Timing Diagram of Transmitter Clock Input with Jitter

Note:

26. This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with

worst jitter ±3ns (cycle-to-cycle) clock input. The specific test methodology is as follows:

27. Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to the right +3ns

when data is HIGH.

28. The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two

clock sources to simulate the worst-case of clock-edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter

at TxCLKOut pin should be measured cross VCC range with 100mV noise (VCC noise frequency <2MHz).

© 2003 Fairchild Semiconductor Corporation

FIN3385 / FIN3386 • Rev. 1.0.6

18

www.fairchildsemi.com

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