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FIN1048M Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de piezaFIN1048M Fairchild
Fairchild Semiconductor Fairchild
componentes Descripción3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
FIN1048M Datasheet PDF : 6 Pages
1 2 3 4 5 6
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms
www.fairchildsemi.com
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General Description
This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data.
The FIN1048 can be paired with its companion driver, the FIN1047, or any other LVDS driver.

Features
■ Greater than 400Mbs data rate
■ Flow-through pinout simplifies PCB layout
■ 3.3V power supply operation
■ 0.4ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Fail safe protection for open-circuit, shorted and terminated conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Pin compatible with equivalent RS-422 and LVPECL devices
■ 16-Lead SOIC and TSSOP packages save space

 

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