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FIN1048M Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de piezaFIN1048M Fairchild
Fairchild Semiconductor Fairchild
componentes Descripción3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
FIN1048M Datasheet PDF : 6 Pages
1 2 3 4 5 6
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
tPLH
tPHL
tTLH
tTHL
tSK(P)
tSK(LH)
tSK(HL)
tSK(PP)
fMAX
Propagation Delay LOW-to-HIGH
Propagation Delay HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Pulse Skew |tPLH - tPHL|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency
(Note 6)
|VID| = 400 mV, CL = 10 pF,
RL = 1k
See Figure 1 and Figure 2
RL = 1k, CL = 10 pF,
see Figure 1 and Figure 2
1.0
2.5
ns
1.0
2.5
ns
0.7
1.2
ns
0.7
1.2
ns
0.4
ns
0.3
ns
1.0
ns
200
375
MHz
tZH
LVTTL Output Enable Time from Z to HIGH
tZL
LVTTL Output Enable Time from Z to LOW
tHZ
LVTTL Output Disable Time from HIGH to Z
tLZ
LVTTL Output Disable Time from LOW to Z
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
RL = 1k, CL = 10 pF,
See Figure 3
6.0
ns
6.0
ns
6.0
ns
6.0
ns
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V.
All channels switching in phase.
Note A: All differential input pulses have frequency = 10MHz, tR or tF = 1ns
Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
VIA
VIB
1.25
1.15
1.15
1.25
2.4
2.3
2.3
2.4
0.1
0
0
0.1
1.5
0.9
0.9
1.5
2.4
1.8
1.8
2.4
0.6
0
0
0.6
Resulting Differential Input
Voltage (mA)
VID
100
100
100
100
100
100
600
600
600
600
600
600
Resulting Common Mode Input
Voltage (V)
VIC
1.2
1.2
2.35
2.35
0.05
0.05
1.2
1.2
2.1
2.1
0.3
0.3
3
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General Description
This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data.
The FIN1048 can be paired with its companion driver, the FIN1047, or any other LVDS driver.

Features
■ Greater than 400Mbs data rate
■ Flow-through pinout simplifies PCB layout
■ 3.3V power supply operation
■ 0.4ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Fail safe protection for open-circuit, shorted and terminated conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Pin compatible with equivalent RS-422 and LVPECL devices
■ 16-Lead SOIC and TSSOP packages save space

 

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