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FIN1028M View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
FIN1028M
Fairchild
Fairchild Semiconductor Fairchild
FIN1028M Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
March 2001
Revised May 2004
FIN1028
3.3V LVDS 2-Bit High Speed Differential Receiver
General Description
This dual receiver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100 mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1028 can be paired with its companion driver, the
FIN1027, or any other LVDS driver.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and
terminated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
Ordering Code:
Order Number Package Number
Package Description
FIN1028M
(Note 1)
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1028K8X
(Preliminary)
MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
FIN1028MPX
(Preliminary)
MLP08C
8-Terminal Molded Leadless Package (MLP) Dual, MO-229, 2mm Square
[TAPE and REEL]
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagrams
Pin Name
ROUT1, ROUT2
RIN1+, RIN2+
RIN1, RIN2
VCC
GND
Description
LVTTL Data Outputs
Non-inverting LVDS Inputs
Inverting LVDS Inputs
Power Supply
Ground
Pin Assignment for SOIC
Function Table
Input
RIN+
RIN+
L
H
H
L
Fail Safe Condition
H = HIGH Logic Level
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
Outputs
ROUT
L
H
H
(Top View)
Terminal Assignments for MLP
(Top Through View)
© 2004 Fairchild Semiconductor Corporation DS500503
www.fairchildsemi.com
 

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