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FCM8202 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
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FCM8202
Fairchild
Fairchild Semiconductor Fairchild
FCM8202 Datasheet PDF : 13 Pages
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Functional Description
Power Management and Regulator
FCM8202 can be operated in a wide input voltage (VPP)
range from 10V to 17.5V. The VOUT pin is the output
terminal of an internal voltage regulator. The typical
output voltage ranges between 5.0V and 5.2V. To
stabilize the VOUT circuit, an external capacitor must be
connected closely between this terminal and the
ground. If the VPP voltage is lower than 8V threshold,
the FCM8202 is shut-down and all the internal registers
are reset.
Clock Generator
FCM8202 comes with a programmable oscillator. Being
determined by an externally added resistor, the system
clock, R_CLK, can be programmed from 960KHz to
1920KHz. The switching frequency of the PWM signal is
equal to 1/64 (divided by 64) of the system clock.
Therefore, when the system clock is configured as
960KHz, PWM is 960KHz / 64 = 15KHz. Similarly, if a
20KHz PWM is intended, the system clock should be
set as 1.28MHz.
PWM Commutation
FCM8202 supports both square-wave PWM and sine-
wave PWM for the BLDC motor control. The controller
comes with the Hall-sensor design used to align the
rotor position of the motor. For Square-Wave Mode, the
PWM output commutation is shown at Table 1.
Table 1. Square Wave Commutation
CW
Hall
Hall
X
000
0
X
111
7
1
001
1
1
011
3
1
010
2
1
110
6
1
100
4
1
101
5
0
101
5
0
100
4
0
110
6
0
010
2
0
011
3
0
001
1
Note:
1. P= PWM, Pb= PWM inverse.
2. X= don’t care.
U-V-W
0-0-0
0-0-0
P-0-0
0-0-P
0-0-P
0-P-0
0-P-0
P-0-0
0-0-P
0-0-P
P-0-0
P-0-0
0-P-0
0-P-0
X-Y-Z
0-0-0
0-0-0
Pb-1-0
0-1-Pb
1-0-Pb
1-Pb-0
0-Pb-1
Pb-0-1
1-0-Pb
0-1-Pb
Pb-1-0
Pb-0-1
0-Pb-1
1-Pb-0
HALL Signals Input
FCM8202 provides a 3~6µs debounce time for each
Hall signal input to reduce the glitch of the Hall signals.
When the transition of the Hall signal is slow, a glitch
might be produced and an error follow. Through a built-
in Hall signal debounce circuit, FCM8202 minimizes the
risk of the glitches and related errors.
PWM Duty Cycle and Operation
The PWM duty is proportional to the voltage levels on
the OPO pin and DUTY pin. A FREE/nST pin is utilized
to enable the PWM signals. When FREE/nST pin is set
as logic HIGH, the PWM state is in Free Mode and all
PWM outputs (U, V, W, X, Y, Z pins) are logic LOW.
Once the FREE/nST pin goes logic LOW, the FCM8202
starts operating the PWM.
Sine-Wave Generator
FCM8202 includes space vector modulation (SVM) for
the sine-wave PWM. An angle-detect circuit phase-
locks the rotor position using the Hall signals of the
motor. The resolution is 32 steps per 60°. Through the
PWM operation, the motor current of each phase is
sine-wave. The angle shift between each phase is 120°.
Figure 17.Sine-Wave Output at CW=1
© 2010 Fairchild Semiconductor Corporation
FCM8202 • Rev. 1.0.0
10
www.fairchildsemi.com
 

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