datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

FAN7685M View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
FAN7685M
Fairchild
Fairchild Semiconductor Fairchild
FAN7685M Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
FAN7685/FAN7686/FAN7687
Application Information
Power Good(PGO) and Power Good Delay
A PC power supply is commonly designed to provide the motherboard with a power good signal, which is defined by the com-
puter manufacturers. If the +3.3V, +5V, and +12V outputs are above the undervoltage threshold limit, the PC power supply
makes the power good signal high. At this time the power supply should be able to provide enough power to assure continuous
operation within the specification. Conversely, when one of the +3.3V, +5V, or +12V outputs falls below the undervoltage
threshold or rises above the overvoltage threshold, or when main power has been turned off for a sufficiently long time so that
power supply operation is no longer assured, a PGO signal will be a low state.
The AC input, power good(PGO), remote on/off(PSON), and +3.3V/+5V/+12V supply rails are shown in the below figure.
T1
VAC
PSON
+12VDC 95%
+5VDC 10%
+3.3VDC
T2
PGO
T3
T4
T5
T6
Although there is no requirement to meet specific timing parameters, the following signal timings are recommended :
-T1(Power On Time) : T1 < 500ms
-T2(Rise Time) : 0.1ms T2 20ms
-T3(PGO Delay) : 100ms < T3 <500ms
-T4(PGO Delay Risetime) : T4 10ms
-T5(AC Loss to PGO Hold-Up Time) : T5 16ms
-T6(Power Down Warning) : T6 1ms
Furthermore, motherboards should be designed to comply with the above recommended timing range. If timings other than
these are implemented or required, that information should be clearly specified.
The FAN7685/FAN7686/FAN7687 provide a power good(PGO) signal for the +3.3V, +5V and +12V supply voltage rails and
a separate power good input(PGI). An internal delay circuit is used to generate a 300ms power good delay.
If voltages at PGI(+1.2V), VS33(+3.3V), VS5(+5V), and VS12(+12V) rise above the undervoltage threshold, the open drain
power good output(PGO) will go high after a delay of 300ms. When the PGI voltage or any of +3.3V, +5V, and +12V rails
drops below the undervoltage threshold, the PGO signal will be disabled immediately.
Power Supply Remote On/Off(PSON) and Fault Protection Output(FPO)
Since the latest personal computer generation focuses on easy turn on and power saving functions, a PC power supply will
require two characteristics. One is a dc power supply remote on/off function; the other is standby power to achieve very low
power consumption of the PC power supply. Thus, the main power needs to be shut down.
The power supply remote on/off(PSON) is an active-low signal that turns on all of the main power rails including the +3.3V,
+5V, and +12V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault
protect output(FPO) also goes high. Thus, the main power rails can not deliver current and are held at 0V.
When the FPO signal is held high due to a fault condition, the fault status will be latched and the outputs of the main power
rails can not deliver current and are held at 0V. Toggling the PSON input signal from low to high will reset the fault protection
latch. During this fault condition only the standby power is not affected.
When the PSON input signal goes from high to low or low to high, the 38ms debounce block will be active to avoid that a
glitch on the PSON input may disable/enable the FPO output. When the PSON is set low, the undervoltage function is disabled
for 75ms to avoid turn-on failure. At turn-off, there is an additional delay of 2.3ms from PSON to FPO.
Power should be delivered to the rails only when the PSON signal is held at ground potential, thus the FPO becomes a low
10
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]