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FAN73892MX View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
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FAN73892MX
Fairchild
Fairchild Semiconductor Fairchild
FAN73892MX Datasheet PDF : 17 Pages
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Electrical Characteristics
VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to
COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are
applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The
VBSUV parameters are referenced to VS1,2,3.
Symbol
Parameter
Over-Current Protection Section
VCSTH+ Over-Current Detect Positive Threshold(4)
VCSTH- Over-Current Detect Negative Threshold(4)
VCSHYS Over-Current Detect Hysteresis(4)
ICSIN
ISOFT
Short-Circuit Input Current
Soft Turn-Off Sink Current
Fault Output Section
VRCINTH+
VRCINTH-
VRCINHYS
IRCIN
VFOL
RCIN Positive-Going Threshold Voltage
RCIN Negative-Going Threshold Voltage
RCIN Hysteresis Voltage
RCIN Internal Current Source
Fault Output Low Level Voltage
RDSRCIN RCIN On Resistance
RDSFO Fault Output On Resistance
Note:
4. These parameters are guaranteed by design.
Condition
VCSIN=1 V
CRCIN=2 nF
VCS=1 V, IFO=1.5 mA
IRCIN=1.5 mA
IFO=1.5 mA
Min. Typ. Max. Unit
400 500 600 mV
440
mV
60
mV
5 10 15 μA
25 40 55 mA
3.3
V
2.6
V
0.7
V
3
5
7 µA
0.2 0.5 V
50 75 100 Ω
90 130 170 Ω
Dynamic Electrical Characteristics
TA=25°C, VBIAS (VDD, VBS1,2,3) = 15.0 V, VS1,2,3 = COM, CRCIN=2 nF, and CLoad = 1000 pF unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
tON Turn-On Propagation Delay
VLIN1,2,3=VHIN1,2,3=5 V, VS1,2,3=0 V 350 500 650
ns
tOFF Turn-Off Propagation Delay
VLIN1,2,3=VHIN1,2,3=0 V, VS1,2,3=0 V 350 500 650
ns
tR Turn-On Rise Time
VLIN1,2,3=VHIN1,2,3=5 V
20 50 100 ns
tF Turn-Off Fall Time
VLIN1,2,3=VHIN1,2,3=0 V
10 30 80 ns
tEN
tCSBLT
Enable LOW to Output Shutdown Delay
CS Pin Leading-Edge Blanking Time(5)
400 500 600 ns
200 300 400 ns
tCSFO Time from CS Triggering to FO(6)
From VCSC=1 V to FO Turn-Off
630
ns
tCSOFF
Time from CS Triggering to All Gate
Outputs Turn-Off(6)
From VCSC=1 V to Starting Gate
Turn-Off
640
ns
tFLTIN Input Filtering Time(7) ( HINx , LINx,,EN)
200 250 300 ns
tFLTCLR Fault-Clear Time
1.3
ms
DT Dead Time
230 290 350 ns
MDT Dead-Time Matching (All Six Channels)
50 ns
MT Delay Matching (All Six Channels)
PM Output Pulse-Width Matching(5,8)
PWIN > 1 µs
50 ns
50 100 ns
Notes:
5. These parameters are guaranteed by design.
6. These parameters are referenced to specified CRCIN(=2 nF), and proportional to value of CRCIN as shown in
Figure 43. It is strongly recommended that the capacitor on RCIN pin should be less than 5 nF.
7. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded.
8. PM is defined as PWIN-PWOUT.
© 2011 Fairchild Semiconductor Corporation
FAN73892 • Rev.1.0.2
6
www.fairchildsemi.com
 

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