FAN5400 View Datasheet(PDF) - Fairchild Semiconductor
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FAN5400
Fairchild Semiconductor
FAN5400 Datasheet PDF : 37 Pages
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Table 23. Register Bit Definitions (Continued)
SP_CHARGER (FAN5403 – FAN5405)
7
Reserved
0
R
6 DIS_VREG
0
R/W
1
5
IO_LEVEL
0
R/W
1
4
SP
0
R
1
0
R
3 EN_LEVEL
1
2:0
VSP
Table 8 R/W
Register Address: 05
Default Value=001X X100
Unused
1.8V regulator is ON
1.8V regulator is OFF
Output current is controlled by IOCHARGE bits
Voltage across RSENSE for output current control is set to 22.1mV (325mA for
RSENSE=68m, 221mA for 100m)
Special charger is not active (VBUS is able to stay above VSP)
Special charger has been detected and VBUS is being regulated to VSP
DISABLE pin is LOW
DISABLE pin is HIGH
Special charger input regulation voltage, see Table 8
SAFETY (FAN5403 – FAN5405)
Register Address: 06
Default Value=0100 0000 (40H)
7
Reserved
0
R Bit disabled and always returns 0 when read back
6:4
ISAFE
Table 9 R/W Sets the maximum IOCHARGE value used by the control circuit, see Table 9
3:0
VSAFE
Table 10 R/W Sets the maximum VOREG used by the control circuit, see Table 10
MONITOR
Register Address: 10H (16)
See Table 19
7 ITERM_CMP
R ITERM comparator output, 1 when VRSENSE > ITERM reference
6 VBAT_CMP
R Output of VBAT comparator
5
LINCHG
R 30mA linear charger ON
4
T_120
See
R
Thermal regulation comparator; when=1 and T_145=0, the charge current is limited
to 22.1mV across RSENSE
3
ICHG
Table 19 R 0 indicates the ICHARGE loop is controlling the battery charge current
2
IBUS
R 0 indicates the IBUS (input current) loop is controlling the battery charge current
1 VBUS_VALID
0
CV
R 1 indicates VBUS has passed validation and is capable of charging
R
1 indicates the constant-voltage loop (OREG) is controlling the charger and all
current limiting loops have released
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
34
www.fairchildsemi.com
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