PWM Controller in Charge Mode
The IC uses a current-mode PWM controller to regulate the
output voltage and battery charge currents. The synchronous
rectifier (Q2) has a negative current limit that turns off Q2 at
140mA to prevent current flow from the battery.
This section references Figure 41 and Figure 42.
At the beginning of charging, the IC starts a 15-minute timer
(t15MIN ). When this timer times out, charging is terminated.
Writing to any register through I2C stops and resets the t15MIN
timer, which in turn starts a 32-second timer (t32S). Setting
the TMR_RST bit (REG0) resets the t32S timer. If the t32S
timer times out, charging is terminated, the registers are set
to their default values, and charging resumes using the
default values with the t15MIN timer running.
Normal charging is controlled by the host with the t32S timer
running to ensure that the host is alive. Charging with the
t15MIN timer running is used for charging that is unattended by
the host. If the t15MIN timer expires, the IC turns off the
charger, sets the CE bit, and indicates a timer fault (110) on
the FAULT bits (REG0[2:0]). This sequence prevents
overcharge if the host fails to reset the t32S timer.
VBUS POR / Non-Compliant Charger Rejection
When the IC detects that VBUS has risen above VIN(MIN)1
(4.4V), the IC applies a 110 load from VBUS to GND. To
clear the VBUS POR (Power-On-Reset) and begin charging,
VBUS must remain above VIN(MIN)1 and below VBUSOVP for
tVBUS_VALID (30ms) before the IC initiates charging. The VBUS
validation sequence always occurs before charging is
initiated or re-initiated (for example, after a VBUS OVP fault
or a VRCH recharge initiation).
tVBUS_VALID ensures that unfiltered 50/60hz chargers and
other non-compliant chargers are rejected.
USB-Friendly Boot Sequence
For all versions except FAN5401, FAN5404
At VBUS POR, when the battery voltage is above the weak
battery threshold (VLOWV), the IC operates in accordance with
its I2C register settings. If VBAT < VLOWV, the IC sets all
registers to their default values and enables the charger
using an input current limit controlled by the OTG pin
(100mA if OTG is LOW and 500mA if OTG is HIGH). This
feature can revive a battery whose voltage is too low to
ensure reliable host operation. Charging continues in the
absence of host communication even after the battery has
reached VOREG, whose default value is 3.54V, and the
charger remains active until t15MIN times out. Once the host
processor begins writing to the IC, charging parameters are
set by the host, which must continually reset the t32S timer to
continue charging using the programmed charging
parameters. If t32S.times out, the register defaults are loaded,
the FAULT bits are set to 110, STAT is pulsed HIGH, and
charging continues with default charge parameters.
The FAN5401 and FAN5404 do not automatically initiate
charging at VBUS POR. Instead, they wait for the host to
initiate charging through I2C commands.
Input Current Limiting
To minimize charging time without overloading VBUS current
limitations, the IC’s input current limit can be programmed by
the IINLIM bits (REG1[7:6]).
Table 7. Input Current Limit
Input Current Limit
For all versions except the FAN5401 and FAN5404, the OTG
pin establishes the input current limit when t15MIN is running.
For the FAN5401 and FAN5404, no charging occurs
automatically at VBUS POR, so the input current limit is
established by the IINLIM bits.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7