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FAN54013UCX View Datasheet(PDF) - Fairchild Semiconductor

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FAN54013UCX Datasheet PDF : 37 Pages
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Table 23. Register Bit Definitions (Continued)
SP_CHARGER (FAN54013-15)
7
Reserved
0
6 DIS_VREG
0
1
0
5
IO_LEVEL
1
0
4
SP
1
0
3 EN_LEVEL
1
2:0
VSP
Table 8
Register Address: 05
Default Value=001X X100
R Unused
R/W 1.8V regulator is ON
1.8V regulator is OFF
R/W Output current is controlled by IOCHARGE bits
Voltage across RSENSE for output current control is set to 22.1mV (325mA for
RSENSE=68m, 221mA for 100m)
R Special charger is not active (VBUS is able to stay above VSP)
Special charger has been detected and VBUS is being regulated to VSP
R DISABLE pin is LOW
DISABLE pin is HIGH
R/W Special charger input regulation voltage, see Table 8
SAFETY (FAN54013-15)
7
Reserved
0
6:4
ISAFE
Table 9
3:0
VSAFE Table 10
MONITOR
7 ITERM_CMP
6 VBAT_CMP
5
LINCHG
4
T_120
See
3
ICHG
Table 19
2
IBUS
1 VBUS_VALID
0
CV
Register Address: 06
Default Value=0100 0000 (40H)
R Bit disabled and always returns 0 when read back
R/W Sets the maximum IOCHARGE value used by the control circuit, see Table 9
R/W Sets the maximum VOREG used by the control circuit, see Table 10
Register Address: 10H (16)
See Table 19
R ITERM comparator output, 1 when VRSENSE > ITERM reference
R Output of VBAT comparator
R 30mA linear charger ON
R
Thermal regulation comparator; when=1 and T_145=0, the charge current is limited
to 22.1mV across RSENSE
R 0 indicates the ICHARGE loop is controlling the battery charge current
R 0 indicates the IBUS (input current) loop is controlling the battery charge current
R 1 indicates VBUS has passed validation and is capable of charging
R
1 indicates the constant-voltage loop (OREG) is controlling the charger and all
current limiting loops have released
© 2011 Fairchild Semiconductor Corporation
FAN5401X Family • Rev. 1.0.2
34
www.fairchildsemi.com
 

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