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FAN54013 View Datasheet(PDF) - Fairchild Semiconductor

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FAN54013 Datasheet PDF : 37 Pages
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I2C Interface
The FAN5401X’s serial interface is compatible with
Standard, Fast, Fast Plus, and High-Speed Mode I2C-Bus®
specifications. The SCL line is an input and the SDA line is a
bi-directional open-drain output; it can only pull down the bus
when active. The SDA line only pulls LOW during data reads
and signaling ACK. All data is shifted in MSB (bit 7) first.
Slave Address
Table 20. I2C Slave Address Byte
Part Types
7654321 0
FAN54010–FAN54014 1 1 0 1 0 1 1 R/W
FAN54015
1 1 0 1 0 1 0 R/W
In hex notation, the slave address assumes a 0 LSB. The
hex slave address for the FAN54015 is D4H and is D6H for
all other parts in the family.
Bus Timing
As shown in Figure 45, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
Data change allowed
SDA
SCL
TH
TSU
Figure 45. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 46.
SDA
THD;STA
Slave Address
MS Bit
A transaction ends with a STOP condition, which is defined
as SDA transitioning from 0 to 1 with SCL HIGH, as shown
in Figure 47.
SDA
Slave Releases
ACK(0) or
NACK(1)
Master Drives
tHD;STO
SCL
Figure 47. Stop Bit
During a read from the FAN5401X (Figure 50), the master
issues a Repeated Start after sending the register address
and before resending the slave address. The Repeated Start
is a 1-to-0 transition on SDA while SCL is HIGH, as shown in
Figure 48.
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) Modes are identical except the bus speed
for HS Mode is 3.4MHz. HS Mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in Fast or Fast Plus Mode
(less than 1MHz clock); slaves do not ACK this transmission.
The master then generates a repeated start condition
(Figure 48) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a stop bit (Figure 47) is
sent by the master. While in HS Mode, packets are
separated by repeated start conditions (Figure 48).
SDA
Slave Releases
ACK(0) or
NACK(1)
tSU;STA
tHD;STA
SLADDR
MS Bit
SCL
Figure 48. Repeated Start Timing
SCL
Figure 46. Start Bit
© 2011 Fairchild Semiconductor Corporation
FAN5401X Family • Rev. 1.0.2
30
www.fairchildsemi.com
 

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