FAN54010 View Datasheet(PDF) - Fairchild Semiconductor
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FAN54010
Fairchild Semiconductor
FAN54010 Datasheet PDF : 37 Pages
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Boost Mode
Boost Mode can be enabled if the IC is in 32-Second Mode
with the OTG pin and OPA_MODE bits as indicated in Table
16. The OTG pin ACTIVE state is 1 if OTG_PL=1 and 0
when OTG_PL=0.
If boost is active using the OTG pin, Boost Mode is initiated
even if the HZ_MODE=1. The HZ_MODE bit overrides the
OPA_MODE bit.
Table 16. Enabling Boost
OTG_EN
OTG
Pin
HZ_
MODE
1
ACTIVE
X
X
X
0
X
ACTIVE
X
0
X
1
1
ACTIVE
1
0
ACTIVE
0
OPA_
MODE
X
1
0
X
1
0
BOOST
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
To remain in Boost Mode, the TMR_RST must be set by the
host before the t32S timer times out. If t32S times out in Boost
Mode; the IC resets all registers, pulses the STAT pin, sets
the FAULT bits to 110, and resets the BOOST bit. VBUS
POR or reading R0 clears the fault condition.
Boost PWM Control
The IC uses a minimum on-time and computed minimum off-
time to regulate VBUS. The regulator achieves excellent
transient response by employing current-mode modulation.
This technique causes the regulator to exhibit a load line.
During PWM Mode, the output voltage drops slightly as the
input current rises. With a constant VBAT, this appears as a
constant output resistance.
The “droop” caused by the output resistance when a load is
applied allows the regulator to respond smoothly to load
transients with no undershoot from the load line. This can be
seen in Figure 33 and Figure 43.
350
325
300
275
250
225
200
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Battery Voltage, VBAT (V)
Figure 43. Output Resistance (ROUT)
VBUS as a function of ILOAD can be computed when the
regulator is in PWM Mode (continuous conduction) as:
VOUT 5.07 ROUT ILOAD
EQ. 1
At VBAT=3.3V, and ILOAD=200mA, VBUS would drop to:
VOUT 5.07 0.26 0.2 5.018V
EQ. 1A
At VBAT=2.7V, and ILOAD=200mA, VBUS would drop to:
VOUT 5.07 0.327 0.2 5.005V
EQ. 1B
PFM Mode
If VBUS > VREFBOOST (nominally 5.07V) when the minimum
off-time has ended, the regulator enters PFM Mode. Boost
pulses are inhibited until VBUS < VREFBOOST. The minimum
on-time is increased to enable the output to pump up
sufficiently with each PFM boost pulse. Therefore the
regulator behaves like a constant on-time regulator, with the
bottom of its output voltage ripple at 5.07V in PFM Mode.
Table 17. Boost PWM Operating States
Mode
Description
Invoked When
LIN
SS
BST
Linear Startup
Boost Soft-Start
Boost Operating Mode
VBAT > VBUS
VBUS < VBST
VBAT > UVLOBST and
SS Completed
Startup
When the boost regulator is shut down, current flow is
prevented from VBAT to VBUS, as well as reverse flow from
VBUS to VBAT.
LIN State
When EN rises, if VBAT > UVLOBST, the regulator first
attempts to bring PMID within 400mV of VBAT using an
internal 450mA current source from VBAT (LIN State). If
PMID has not achieved VBAT – 400mV after 560s, a FAULT
state is initiated.
SS State
When PMID > VBAT – 400mV, the boost regulator begins
switching with a reduced peak current limit of about 50% of
its normal current limit. The output slews up until VBUS is
within 5% of its setpoint; at which time, the regulation loop is
closed and the current limit is set to 100%.
If the output fails to achieve 95% of its setpoint (VBST) within
128s, the current limit is increased to 100%. If the output
fails to achieve 95% of its setpoint after this second 384s
period, a fault state is initiated.
© 2011 Fairchild Semiconductor Corporation
FAN5401X Family • Rev. 1.0.2
27
www.fairchildsemi.com
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