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FAN2558MP18X View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
FAN2558MP18X
Fairchild
Fairchild Semiconductor Fairchild
FAN2558MP18X Datasheet PDF : 15 Pages
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PRODUCT SPECIFICATIONS
FAN2558/FAN2559
Control Functions
Enable Pin
Connecting 2V or greater to the Enable pin will enable the
output, while 0.4V or less will disable it while reducing the
quiescent current consumption to less than 1µA. If this shut-
down function is not needed, the pin can simply be con-
nected permanently to the VIN pin. Allowing this pin to oat
will cause erratic operation.
Error Flag (Power Good)
Fault conditions such as input voltage dropout (low VIN),
overheating, or overloading (excessive output current), will
set an error ag. The PG pin which is an open-drain output,
will go LOW when VOUT is less than 95% or the specied
output voltage. When the voltage at VOUT is greater than
95% of the specied output voltage, the PG pin is HIGH. A
logic pull-up resistor of 47Kis recommended at this out-
put. The pin can be left disconnected if unused.
Thermal Protection
The FAN2558/FAN2559 is designed to supply high peak
output currents for brief periods, however sustained exces-
sive output load at high input - output voltage difference will
increase the device’s temperature and exceed maximum rat-
ings due to power dissipation. During output overload condi-
tions, when the die temperature exceeds the shutdown limit
temperature of 150°C, an onboard thermal protection will
disable the output until the temperature drops approximately
10°C below the limit, at which point the output is re-enabled.
During a thermal shutdown, the user may assert the power-
down function at the Enable pin, reducing power consump-
tion to a minimum.
Thermal Characteristics
The FAN2558/FAN2559 is designed to supply 180mA at the
specied output voltage with an operating die (junction)
temperature of up to 125°C. Once the power dissipation and
thermal resistance is known, the maximum junction tempera-
ture of the device can be calculated. While the power dissipa-
tion is calculated from known electrical parameters, the
actual thermal resistance depends on the thermal characteris-
tics of the SOT23-5 surface-mount package and the sur-
rounding PC board copper to which it is mounted.
The power dissipation is equal to the product of the input-to-
output voltage differential and the output current plus the
ground current multiplied by the input voltage,
or:
PD = (VIN – VOUT) × IOUT + VIN × IGND
The ground pin current IGND can be found in the charts
provided in the Electrical Characteristics section.
The relationship describing the thermal behavior of the
package is:
PD(max)
=
T----J---(-m----θa---xJ---A)---–----T----A--
where TJ(max) is the maximum allowable junction tempera-
ture of the die, which is 125°C, and TA is the ambient operat-
ing temperature. θJA is dependent on the surrounding PC
board layout and can be empirically obtained. While the θJC
(junction-to-case) of the SOT23-5 package is specied at
130°C /W, the θJA of the minimum PWB footprint will be at
least 235°C /W. This can be improved by providing a heat
sink of surrounding copper ground on the PWB. Depending
on the size of the copper area, the resulting θJA can range
from approximately 180°C /W for one square inch to nearly
130°C /W for 4 square inches. The addition of backside cop-
per with through-holes, stiffeners, and other enhancements
can also aid in reducing thermal resistance. The heat contrib-
uted by the dissipation of other devices located nearby must
be included in the design considerations. Once the limiting
parameters in these two relationships have been determined,
the design can be modied to ensure that the device remains
within specied operating conditions. If overload conditions
are not considered, it is possible for the device to enter a
thermal cycling loop, in which the circuit enters a shutdown
condition, cools, re-enables, and then again overheats and
shuts down repeatedly due to an unmanaged fault condition.
Adjustable Version
The FAN2558ADJ includes an input pin ADJ which allows
the user to select an output voltage ranging from 1V to near
VIN, using an external resistor divider. The voltage VADJ pre-
sented to the ADJ pin is fed to the onboard error amplier
which adjusts the output voltage until VADJ is equal to the
onboard bandgap reference voltage of 1.00V(typ). The equa-
tion is:
VOUT = 0.59V ×
1 + -R----1
R2
Since the bandgap reference voltage is trimmed, 1% initial
accuracy can be achieved. The total value of the resistor
chain should not exceed 250KOhm total to keep the error
amplier biased during no-load conditions. Programming
output voltages very near VIN need to allow for the magni-
tude and variation of the dropout voltage VDO over load, sup-
ply, and temperature variations. Note that the low-leakage
FET input to the CMOS error amplier induces no bias
current error to the calculation.
REV. 1.0.4 3/15/04
7
 

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