FAN100MY View Datasheet(PDF) - Fairchild Semiconductor

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FAN100MY

Primary-Side-Control PWM Controller

Fairchild Semiconductor 

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike occurs at the sense resistor. To avoid premature

termination of the switching pulse, a leading-edge

blanking time is built in. Conventional RC filtering can be

omitted. During this blanking period, the current-limit

comparator is disabled and cannot switch off the gate

driver.

Built-in Slope Compensation

The sensed voltage across the current-sense resistor is

used for current-mode control and pulse-by-pulse

current limiting. Built-in slope compensation improves

stability and prevents sub-harmonic oscillations due to

peak-current mode control. The FAN100 has a

synchronized, positively-sloped ramp built-in at each

switching cycle.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally at

16V and 5V. During start-up, the hold-up capacitor must

be charged to 16V through the startup resistor to enable

the FAN100. The hold-up capacitor continues to supply

VDD until power can be delivered from the auxiliary

winding of the main transformer. VDD must not drop

below 5V during this startup process. This UVLO

hysteresis window ensures that hold-up capacitor is

adequate to supply VDD during start-up.

Noise Immunity

Noise from the current sense or the control signal can

cause significant pulse-width jitter, particularly in

continuous-conduction mode. While slope

compensation helps alleviate these problems, further

precautions should still be taken. Good placement and

layout practices should be followed. Avoiding long PCB

traces and component leads, locating compensation

and filter components near the FAN100, and increasing

the power MOS gate resistance are advised.

VDD Over-Voltage Protection (OVP)

VDD over-voltage protection prevents damage due to

over-voltage conditions. When the voltage VDD exceeds

28V due to abnormal conditions, PWM pulses are

disabled until the VDD voltage drops below the UVLO,

then starts up again. Over-voltage conditions are usually

caused by open feedback loops.

Over-Temperature Protection (OTP)

The built-in temperature-sensing circuit to shut down

PWM output once the junction temperature exceeds

140°C. While PWM output is shut down, the VDD voltage

gradually drops to the UVLO voltage. Some of the

FAN100’s internal circuits are shut down and VDD

gradually starts increasing again. When VDD reaches

16V, all the internal circuits, including the temperature

sensing circuit, start operating normally. If the junction

temperature is still higher than 140°C, the PWM

controller shuts down immediately. This situation

continues until the temperature drops below 110°C.

Gate Output

The BiCMOS output stage is a fast totem pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

15V Zener diode to protect power MOSFET transistors

against undesired over-voltage gate signals.

© 2008 Fairchild Semiconductor Corporation

FAN100 Rev. 1.0.0

11

www.fairchildsemi.com

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