EBE10RD4ABFA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
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EBE10RD4ABFA Datasheet PDF : 22 Pages
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EBE10RD4ABFA
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
Number of row address
0 0 0 0 1 1 1 0 0EH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM ranks
0 1 1 0 0 0 0 0 60H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-5C
0 0 1 1 1 1 0 1 3DH
-4A
SDRAM access from clock (tAC)
-5C
0 1 0 1 0 0 0 0 50H
0 1 0 1 0 0 0 0 50H
-4A
0 1 1 0 0 0 0 0 60H
DIMM configuration type
0 0 0 0 0 0 1 0 02H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 0 1 0 0 04H
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
Reserved
0 0 0 0 0 0 0 0 00H
DIMM type information
0 0 0 0 0 0 0 1 01H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 1 1 0 0 0 0 30H
Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH
-5C
-4A
0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 4
0 1 0 1 0 0 0 0 50H
-5C
-4A
0 1 1 0 0 0 0 0 60H
Minimum clock cycle time at CL = 3
-5C, -4A
0
1
0
1
0
0
0
0
50H
Maximum data access time (tAC) from
clock at CL = 3
0 1 1 0 0 0 0 0 60H
-5C, -4A
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
11
1
72
0
SSTL 1.8V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
ECC
7.8µs
×4
×4
0
4,8
4
3, 4, 5
0
Registered
Normal
VDD ± 0.1V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
0.6ns*1
Data Sheet E0366E70 (Ver. 7.0)
5
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