DS_K6X8016C3B View Datasheet(PDF) - Samsung

Part Name

Description

View to exact match

DS_K6X8016C3B

512Kx16 bit Low Power Full CMOS Static RAM

Samsung 

K6X8016C3B Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

Address

Data Out

tRC

tAA

tOH

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

tRC

tAA

tCO

tBA

UB, LB

OE

Data out

High-Z

tOE

tOLZ

tBLZ

tLZ

tOH

Data Valid

tHZ

tBHZ

tOHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

6

Revision 1.0

September 2003

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