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54LS109 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54LS109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs National-Semiconductor
National ->Texas Instruments National-Semiconductor
54LS109 Datasheet PDF : 6 Pages
1 2 3 4 5 6
June 1989
54LS109 DM54LS109A DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K flip-flops with complementary outputs The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of
the clock The data on the J and K inputs may be changed
while the clock is high or low as long as setup and hold
times are not violated A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs
Features
Y Alternate Military Aerospace device (54LS109) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6368 – 1
Order Number 54LS109DMQB 54LS109FMQB DM54LS109AJ
DM54LS109AW DM74LS109AM or DM74LS109AN
See NS Package Number J16A M16A N16E or W16A
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L
H
X
XX
H
L
H
L
X
XX
L
H
L
L
X
XX H
H
H
H
u
LL
L
H
H
H
u HL
Toggle
H
H
u
L
H
Q0
Q0
H
H
u HH H
L
H
H
L
X
X
Q0
Q0
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
u e Rising Edge of Pulse
e This configuration is nonstable that is it will not persist when preset
and or clear inputs return to their inactive (high) state
Q0 e The output logic level of Q before the indicated input conditions were
established
Toggle e Each output changes to the complement of its previous level on
each active transition of the clock pulse
C1995 National Semiconductor Corporation TL F 6368
RRD-B30M105 Printed in U S A
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