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DAC8043FZ View Datasheet(PDF) - Analog Devices

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DAC8043FZ Datasheet PDF : 12 Pages
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DAC8043
DAC8043 INTERFACE TO THE 8085
The DAC8043’s interface to the 8085 microprocessor is shown
in Figure 10. Note that the microprocessor’s SOD line is used
to present data serially to the DAC.
Data is clocked into the DAC8043 by executing memory write
instructions. The clock input is generated by decoding address
8000 and WR. Data is loaded into the DAC register with a
memory write instruction to address A000.
Serial data supplied to the DAC8043 must be present in the
right justified format in registers H and L of the microprocessor.
Figure 8. Analog/Digital Divider
INTERFACING TO THE MC6800
As shown in Figure 9, the DAC8043 may be interfaced to the
6800 by successively executing memory WRITE instructions
while manipulating the data between WRITEs, so that each
WRITE presents the next bit.
In this example the most significant bits are found in memory
location 0000 and 0001. The four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. The data is taken from the
DB7 line.
The serial data loading is triggered by the CLK pulse which is
asserted by a decoded memory WRITE to memory location
2000, R/W, and φ2. A WRITE to address 4000 transfers data
from input register to DAC register.
Figure 10. DAC8043-8085 Interface
DAC8043 TO 68000 INTERFACING
The DAC8043 interfacing to the 68000 microprocessor is
shown in Figure 11. Again, serial data to the DAC is taken from
one of the microprocessor’s data bus lines.
Figure 9. DAC8043–MC6800 Interface
Figure 11. DAC8043–68000 µP Interface
–10–
REV. C
 

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