|DAC3151||Single 14-/12-/10-Bit 500 MSPS Digital-to-Analog Converters|
|DAC3151 Datasheet PDF : 57 Pages |
SLAS959A – AUGUST 2013 – REVISED AUGUST 2013
Register name: config127– Address: 0x7F, Default: 0x0045
A fixed ‘1’ that can be used to test the Voh at the SIF output.
A fixed ‘0’ that can be used to test the Vol at the SIF output.
Fixed at "01".
There are three modes of syncing included in the DAC3151/DAC3161/DAC3171.
• NORMAL Dual Sync – The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0)
sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value.
Multiple chip alignment can be accomplished with this kind of syncing.
• SYNC ONLY – In this mode only the SYNC pin is used to sync both the read and write pointers of the FIFO.
There is an asynchronized handoff between the DATACLK and DACCLK when using this mode, therefore it is
impossible to accurately align multiple chips closer than 2 or 3T.
• SIF_SYNC – When neither SYNC nor ALIGN are used, a programmable SYNC pulse can be used to sync
the design. However, the same issues as ISTROBE ONLY apply. There is an asynchronized handoff between
the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of the SIF_SYNC
it is impossible to align the sync up with any sample at the input. Note: SIF_SYNC mode is the only
synchronisation mode supported in the 7-bit interface mode.
Note: When ALIGNP/N are not used, it is recommended to clear the alignrx_ena register (config1, bit 4),
and tie ALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP/N are not used, it is recommended
to clear register lvdssyncrx_ena (config0, bit3), and the unused SYNCP/N pins can be left open or tied to
DAC3151/DAC3161/DAC3171 includes flexible alarm monitoring that can be used to alert a possible malfunction
scenario. All alarm events can be accessed either through the SIP registers and/or through the ALARM pin.
Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to
allow further testing. The set of alarms includes the following conditions:
Zero check alarm
• Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a
shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a
sync to the FIFO block is required.
• alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
• alarm_fifo_2away. Pointers are within two addresses of each other.
• alarm_fifo_1away. Pointers are within one address of each other.
• alarm_fifo_collision. Pointers are equal to each other.
• clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
• alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
• alarm_dataclk_gone. Occurs when the DATACLK has been stopped.
Pattern checker alarm
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